Friday, 15 June 2012

RAM VLSI CODE



//RAM
module ram( we, en, addr, di, dout);
input        we;
input        en;
input  [4:0] addr;
input  [3:0] di;
output [3:0] dout;
reg    [3:0] RAM [31:0];
reg    [3:0] dout;
always @(en)
                begin
                   if (en) begin
                      if (we)
                                 RAM[addr] <= di;
                      else
                                 dout <= RAM[addr];
                   end
                end
endmodule


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