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Tuesday 7 June 2016


In this post, let us see the timescale feature and system tasks that are available in Verilog HDL with brief examples.

`timescale directive specifies the time unit and time precision of the modules that follow it. The time unit is the unit of measurement for time values such as the simulation time and delay values.
Syntax:   `timescale <time_unit>/<time_precision>
              The time_unit argument specifies the unit of measurement for times and delays.
The time_precision argument specifies how delay values are rounded before being used in simulation. The smallest time_precision argument of all the 'timescale compiler directives in the design determines the precision of the time unit of the simulation.

The time_precision argument shall be at least as precise as the time_unit argument; it cannot specify a longer unit of time than time_unit. The integers in these arguments specify an order of magnitude for the size of the value; the valid integers are 1, 10, and 100. The character strings "s, ms, us, ns, ps, and fs " represent units of measurement;

Example: `timescale 1ns/100ps
                Here in the above example, time_unit is 1ns & time_precision is 100ps. So the delay of #1 in the code is equivalent to 1ns delay in simulation. The delay of #1.56 will be rounded to 1.6ns. i.e. the decimal fraction will be rounded to in multiples of the time_precision value. Each #delay value is rounded to time delays w.r.t the timescale specified and added to the current simulation time.

Some of the system tasks on timescale are
·         $printtimescale() prints the timescale settings of the current scope of the file.
·         $timeformat(..,..,,,) system task

The $timeformat system task performs the following two operations:
Ø  It sets the time unit for all later-entered delays entered interactively.
Ø  It sets the time unit, precision number, suffix string, and minimum field width for all %t formats specified in all modules that follow in the source description until another $timeformat system task is invoked.

Syntax for $timeformat is
$timeformat ( units_number , precision_number , suffix_string , minimum_field_width ) ;

Example: $timeformat(-9,3,"ns",8);   This will display any %t string in ns with 3 digits precision, and 8 characters string size.

Let us see the code for the example used for different timescale settings & $timeformat system task.
initial begin
    #1     $display("\n1) %t",$realtime); 
    #10.5  $display("\n2) %t",$realtime); 
    #10.56 $display("\n3) %t",$realtime);
    #10.56 $display("\n4) %t",$realtime);
    #11.46 $display("\n5) %t",$realtime);

The output of the above code with different timescale values are illustrated in the below table.
`timescale 1ns/1ps
`timescale 1ns/10ps
`timescale 1ns/100ps
1)  1.000ns
2) 11.500ns
3) 22.060ns
4) 32.620ns
5) 44.080ns
1)  1.000ns
2) 11.500ns
3) 22.060ns
4) 32.620ns
5) 44.080ns
1)  1.000ns
2) 11.500ns
3) 22.100ns
4) 32.700ns
5) 44.200ns

The calculation for timescale 1ns/100ps is as below:
1.       Step 1, time is 1ns
2.       Step 2, time is (1ns+10.5ns)=11.5ns
3.       Step 3, time is (11.5ns + 10.6ns) = 22.1ns
4.       Step 4, time is (22.1ns + 10.6ns) = 32.7ns
5.       Step 5, time is (32.7ns + 11.5ns) = 44.2ns

 Similarly you could calculate for different timescale values. If you've any queries, plz do comment it.

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Tuesday 5 April 2016

Perl – File Read Write Example

Perl – File Read Write Example

In this post, let’s see how to remove the new line character or line break in a text file and save the result in another text file.

Refer to other posts File handling, RegEx.

To accomplish the removal of new line character, we use RegEx substitution operator. The code for substitution is as below,
    $a =~ s/\n//;   # $a is the variable in which the replacement takes place

·         The input to the script is through command line arguments. The command line inputs are stored in the array variable @ARGV (please note the CAPS). First we check the size. If no command line arguments is specified, the size of ARGV is -1. If so, the script prints the usage & exits, using the in-built function die().

unless($#ARGV <0) {
} else {
    die "\nUsage:\n remove_new_line.pl <input_file>\n";

·         If valid input is provided, then open the specified file in read mode as below. If unable to open the file, exit with a note printed.  $! Is the Perl system variable which prints the error from the OS.
  open FIN, "<$in_file" or die "Unable to read '$in_file' :$!";

·         Create the output file by appending the name “new_” to the input file name.
open FOUT, ">new_$in_file" or die "Unable to create 'new_$in_file' :$!";

·         Then create a loop, that executes for each line of the input file. Then remove the newline character and write back the result to output file.
while ($a=<FIN>) {
  # remove \n character
    $a =~ s/\n//;
  # write the new data to text file
    print FOUT $a;

Sample output of this script:
            Top file is the input & bottom file is the output.

Monday 14 March 2016

Perl string manipulation with examples

  Perl offers many easier ways to manipulate string, which is yet powerful with RegEx. In this post, the various functions available in Perl for string manipulation is explained with examples. 

Saturday 12 March 2016

Perl Regular expression - Perl RegEx with examples

   A regular expression or RegEx is a string of characters that define the pattern or patterns you are viewing. The syntax of regular expressions in Perl is very similar to what you will find within other regular expression, supporting programs, such as sedgrep, and awk

   In this post, Perl regex is illustrated with examples.

Friday 11 March 2016

Glitch Free Clock Gating - verilog good clock gating

   Clock gating is a popular technique used in many synchronous circuits for reducing dynamic power dissipation. This saves power by adding more logic to a circuit to the clock by disabling clock switching, so that the flip-flops in them do not have to switch states. As a result, the switching power consumption goes to zero, and only leakage currents are incurred.

   Clock gating logic can be added into a design in a variety of ways:
  1. Coded into the RTL code as enable conditions that can be automatically translated into clock gating logic by synthesis tools.
  2. Inserted into the design manually by the RTL designers (typically as module level clock gating) by instantiating library specific ICG (Integrated Clock Gating) cells to gate the clocks of specific modules or registers.
  3. Semi-automatically inserted into the RTL by automated clock gating tools. These tools either insert ICG cells into the RTL, or add enable conditions into the RTL code. These typically also offer sequential clock gating optimisations.
   Poor clock gating produces glitches in the output clock, making unwanted clock transitions which may lead to timing violations,etc., and increased power consumption.
   Here is an Verilog example illustrating the RTL code for clock gating & its issues.

The below code produces simple clock gating mechanism with an 2-input AND gate, with inputs as CLK & CLK_EN. But the greatest disadvantage is that it produces glitches in output as in the below waveform.
//BAD clock gating, can cause glitches in output
 assign clk_out1 = c_en && clk;

To overcome the glitches, a latching needs to be added to change the enable only when CLK is high/low. By this way, glitches are avoided & produces a good clock for the rest of the block. 
//GOOD clock gating & glitch free
 always @ (c_en or clk) begin
     if (!clk)
        en_out2 = c_en; // build latch
 assign clk_out2 = en_out2 && clk;

Circuit synthesized for the above codes:
Verilog RTL - Clock gating- circuit :: ELecDude

Waveform for the above code:

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