Based on the simulation, when the condition is X conditional operator outputs X whereas if statement outputs else part. Except this, moreover no difference in execution of these two.
In this post, let us see the timescale feature and system tasks that are available in Verilog HDL with brief examples.
`timescale directive specifies the time unit and time precision of the modules that follow it. The time unit is the unit of measurement for time values such as the simulation time and delay values.
Syntax: `timescale <time_unit>/<time_precision>
The time_unit argument specifies the unit of measurement for times and delays.
The time_precision argument specifies how delay values are rounded before being used in simulation. The smallest time_precision argument of all the 'timescale compiler directives in the design determines the precision of the time unit of the simulation.
The time_precision argument shall be at least as precise as the time_unit argument; it cannot specify a longer unit of time than time_unit. The integers in these arguments specify an order of magnitude for the size of the value; the valid integers are 1, 10, and 100. The character strings "s, ms, us, ns, ps, and fs " represent units of measurement;
Example: `timescale 1ns/100ps
Here in the above example, time_unit is 1ns & time_precision is 100ps. So the delay of #1 in the code is equivalent to 1ns delay in simulation. The delay of #1.56 will be rounded to 1.6ns. i.e. the decimal fraction will be rounded to in multiples of the time_precision value. Each #delay value is rounded to time delays w.r.t the timescale specified and added to the current simulation time.
Some of the system tasks on timescale are
·$printtimescale() prints the timescale settings of the current scope of the file.
·$timeformat(..,..,,,) system task
The $timeformat system task performs the following two operations:
ØIt sets the time unit for all later-entered delays entered interactively.
ØIt sets the time unit, precision number, suffix string, and minimum field width for all %t formats specified in all modules that follow in the source description until another $timeformat system task is invoked.
Clock gating is a popular technique used in many synchronous circuits for reducing dynamic power dissipation. This saves power by adding more logic to a circuit to the clock by disabling clock switching, so that the flip-flops in them do not have to switch states. As a result, the switching power consumption goes to zero, and only leakage currents are incurred.
Clock gating logic can be added into a design in a variety of ways:
Coded into the RTL
code as enable conditions that can be automatically translated into
clock gating logic by synthesis tools.
Inserted into the design manually by the RTL designers (typically as
module level clock gating) by instantiating library specific ICG
(Integrated Clock Gating) cells to gate the clocks of specific modules
or registers.
Semi-automatically inserted into the RTL by automated clock gating
tools. These tools either insert ICG cells into the RTL, or add enable
conditions into the RTL code. These typically also offer sequential
clock gating optimisations.
Poor clock gating produces glitches in the output clock, making unwanted clock transitions which may lead to timing violations,etc., and increased power consumption.
Here is an Verilog example illustrating the RTL code for clock gating & its issues.
The below code produces simple clock gating mechanism with an 2-input AND gate, with inputs as CLK & CLK_EN. But the greatest disadvantage is that it produces glitches in output as in the below waveform.
//BAD clock gating, can cause glitches in output assign clk_out1 = c_en && clk;
To overcome the glitches, a latching needs to be added to change the enable only when CLK is high/low. By this way, glitches are avoided & produces a good clock for the rest of the block.
//GOOD clock gating & glitch free always @ (c_en or clk) begin if (!clk) en_out2 = c_en; // build latch end assign clk_out2 = en_out2 && clk;
A
real-time clock (RTC) is a computer clock (most often in the form of an
integrated circuit) that keeps track of the current time. Although the term
often refers to the devices in personal computers, servers and embedded systems,
RTCs are present in almost any electronic device which needs to keep accurate
time. The term is used to avoid confusion with ordinary hardware clocks which
are only signals that govern digital electronics, and do not count time in
human units.
Here we've designed an RTC module
using Verilog which is very much similar to that of the RTC Chips, but it is a
RTL design. This RTL RTC module can be
compiled into a FPGA or PLDs. This module takes up 1Hz clock & starts
clocking once enabled. Note that it is a simple design which does not keep the
time running when powered off.
This
module is divided into two parts namely, rtc and clock divider. The clock
divider module receives the global FPGA clock (say 20MHz) and produces 1Hz
clock for the rtc module, which keep track of time.
The codes are self-explained. If you've any doubts or need any
clarifications, plz don't hesitate to ask us through comments or by mail (admin@elecdude.com).
