SPI means Serial Peripheral Interface.
The Serial Peripheral Interface Bus or SPI bus is a synchronous serial data link de facto standard, named by Motorola, that operates in full duplex mode. Devices communicate in master/slave mode where the master device initiates the data frame. Multiple slave devices are allowed with individual slave select (chip select) lines. Sometimes SPI is called a four-wire serial bus, contrasting with three-, two-, and one-wire serial buses. SPI is often referred to as SSI (Synchronous Serial Interface).
The SPI Mode 3 waveform is
We have seen the working of SPI and the SPI Master in the previous page. Now let us see about the SPI Slave.Click here to goto SPI MASTER Page.
SPI SLAVE VERILOG MODULE:
The slave module is simple. It is just like a shift register with additional control signal SS_bar. The data is sampled in at positive edge of SCK and shifted out at negative edge of SCK. The data transmission of slave is active only when SS_bar input signal is low, otherwise it is disconnected from the bus & Sdout is tri-stated. Other control signals are similar to that of SPI Master Module.
SPI Slave Block Diagram is
The SPI Slave module verilog code is as follows:
//read from sdin
always @(posedge sck or negedge rstb)
begin
if (rstb==0)
begin rreg = 8'h00; rdata = 8'h00; done = 0; nb = 0; end //
else if (!ss) begin
if(mlb==0)
begin rreg ={sdin,rreg[7:1]}; end
else
begin rreg ={rreg[6:0],sdin}; end
nb=nb+1;
if(nb!=8) done=0;
else begin rdata=rreg; done=1; nb=0; end
end
end
//send to sdout
always @(negedge sck or negedge rstb)
begin
if (rstb==0)
begin treg = 8'hFF; end
else begin
if(!ss) begin
if(nb==0) treg=tdata;
else begin
if(mlb==0)
begin treg = {1'b1,treg[7:1]}; end
else
begin treg = {treg[6:0],1'b1}; end
end
end //!ss
end //rstb
end //always
//read from sdin
always @(posedge sck or negedge rstb)
begin
if (rstb==0)
begin rreg = 8'h00; rdata = 8'h00; done = 0; nb = 0; end //
else if (!ss) begin
if(mlb==0)
begin rreg ={sdin,rreg[7:1]}; end
else
begin rreg ={rreg[6:0],sdin}; end
nb=nb+1;
if(nb!=8) done=0;
else begin rdata=rreg; done=1; nb=0; end
end
end
//send to sdout
always @(negedge sck or negedge rstb)
begin
if (rstb==0)
begin treg = 8'hFF; end
else begin
if(!ss) begin
if(nb==0) treg=tdata;
else begin
if(mlb==0)
begin treg = {1'b1,treg[7:1]}; end
else
begin treg = {treg[6:0],1'b1}; end
end
end //!ss
end //rstb
end //always
Hey What s the significance of "tdat" in Slave module... i'm not getting... can you explain me abt tat plz....
ReplyDeleteVery nice tutorial, but I was wondering where is the link for spi slave, master and test-bench. The link provided is broken.
ReplyDelete