Tuesday, 12 June 2012

UP/DOWN COUNTER: VHDL CODE



UP/DOWN COUNTER:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity UP_DOWN_COUNTER is
    Port ( clk : in  STD_LOGIC;
           rst : in  STD_LOGIC;
           UD : in  STD_LOGIC;
           Q : out  STD_LOGIC_VECTOR (3 downto 0));
end UP_DOWN_COUNTER;

architecture Behavioral of UP_DOWN_COUNTER is
signal tmp:STD_LOGIC_VECTOR (3 downto 0);
begin
process(clk,rst)
begin
if(rst='1') then
tmp<="0000";
elsif(clk'event and clk='1') then
if(UD='1') then
tmp<=tmp+1;
else
tmp<=tmp-1;
end if;
end if;
end process;
Q <= tmp;
end Behavioral;

Reactions:

2 comments:

Post a Comment

Search Here...