Saturday 5 October 2013

VHDL File I/O - File read write code example

     Here we present the VHDL File I/O syntax and examples.

     This is very useful in handling file i/o for processing signals, images into VHDL codes.


VHDL File operations:

  • File open
  • File read/write
  • File close
The file i/o procedures and commands are under IEEE -> STD_LOGIC_TEXTIO
library IEEE;

File open syntax:

file <FILEPOINTER> : text is in "<FILENAME>";
File Read Syntax:

procedure READLINE(file F: TEXT; L: out LINE);
procedure READ(L: inout LINE; value: out bit);
-- line serves as a buffer for the data to be written/read  into/from  a file

    variable <inline>: line;

    variable <dataread> : real;

    readline(<infileptr>, <inline>);
    read(<inline>, <dataread>);
Then this real value can be converted into required datatype.

File Write Syntax:

procedure WRITELINE(file F: TEXT; L: inout LINE);
procedure WRITE(L: inout LINE; value: out bit);

    variable <inline>: line;

    variable <datas> : real;
    variable <dataint> : integer;

   write(<inline>, <datas>);   --writes real
writeline(<infileptr>, <inline>);

   write(<inline>, <dataint>);  -- writes integer
writeline(<infileptr>, <inline>);

For checking current line as end-of-file:

For writing string & bitvector:

WRITE (buf, string’("hello"));
WRITE (buf, bit_vector’("010111"));

Example for file read & write as a PROCESS:

din:STD_LOGIC_VECTOR(7 downto 0);
d1,intt,linenumber: integer;

reading : process

    file infile : text is in "file1.txt"; --declare input file 1987
    variable inline: line; --line number declaration
    variable dataread1 : real;
        wait until clk = '1' and clk'event;
            if (not (endfile(infile)) then
                    readline(infile, inline);
                    read(inline, dataread1);
                    d1 <=integer(dataread1);
                endoffile <='1'; --set signal to tell end of file read file is reached.
        end if;
    end process reading;

writing : process
    file outfile : text is out "outimgvhdl.txt";
    variable buff_out : line; --line number declaration
        wait until clk = '1' and clk'event;
        if(endoffile='0') then --if the file end is not reached.
            write(buff_out, intt);             --writes integer
            writeline(outfile, buff_out);

            write(buff_out, din);             --writes STD_LV
            writeline(outfile, buff_out);

            write(buff_out, dreal);             --writes real data (float)
            writeline(outfile, buff_out);
          end if;   
            linenumber <= linenumber + 1;
        end if;
    end process writing;

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  1. tanks a lot for your very very useful website & tutorials! :)
    I am doing a project in which I need to receive an image from an Arm microcontroller and deliver it to an FPGA . I do not know how FPGA receive an image. :(
    Should I convert image to an array? or text file? or ....
    Is it possible to mail me a code for doing this part? or let me know if you have explain sth about this question in your site.
    thanks :)

    1. plz post it our vlsi team will reply soon,

    2. see vhdl image adding..... " "


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