//7 SEG
module segx(s,d);
input [2:0] d;
output[8:0] s;
reg [8:0] s;
always @(d)
case(d)
3'b000: s <= 9'b000000011;
3'b001: s <= 9'b010011111;
3'b010: s <= 9'b000100101;
3'b011: s <= 9'b000001101;
3'b100: s <= 9'b010011001;
3'b101: s <= 9'b001001001;
3'b110: s <= 9'b001000001;
3'b111: s <= 9'b000011111;
endcase
endmodule
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