BOOTH MULTIPLIER VLSI CODE

//BOOTH MULTIPLIER

module booth #(parameter WIDTH=4)

 (  input     clk,

    input     enable,

    input    [WIDTH-1:0] multiplier,                           

    input    [WIDTH-1:0] multiplicand,

   output reg [2*WIDTH-1:0] product);

parameter          IDLE       = 2'b00,                                // state encodings

ADD   = 2'b01,

                SHIFT     = 2'b10,

                OUTPUT = 2'b11;

reg  [1:0]              current_state, next_state;  // state registers.

reg  [2*WIDTH+1:0] a_reg,s_reg,p_reg,sum_reg;  // computational values.

reg  [WIDTH-1:0]      iter_cnt;          // iteration count for determining when done.

wire [WIDTH:0]                    multiplier_neg;  // negative value of multiplier

always @(posedge clk)

  if (!enable) current_state = IDLE;

  else         current_state = next_state;

always @* begin

next_state = 2'bx;

case (current_state)

   IDLE: if (enable)  next_state = ADD;

            else  next_state = IDLE;

   ADD:  next_state = SHIFT;

   SHIFT: if (iter_cnt==WIDTH) next_state = OUTPUT;

              else   next_state = ADD;

   OUTPUT:  next_state = IDLE;

endcase

end

// negative value of multiplier.

assign multiplier_neg = -{multiplier[WIDTH-1],multiplier};

// algorithm implemenation details.

always @(posedge clk) begin

  case (current_state)

    IDLE :  begin

                        a_reg    <= {multiplier[WIDTH-1],multiplier,{(WIDTH+1){1'b0}}};

                        s_reg    <= {multiplier_neg,{(WIDTH+1){1'b0}}};

                        p_reg    <= {{(WIDTH+1){1'b0}},multiplicand,1'b0};

                        iter_cnt <= 0;

                     end

    ADD  :  begin

                                case (p_reg[1:0])

                                  2'b01       : sum_reg <= p_reg+a_reg;

                                  2'b10       : sum_reg <= p_reg+s_reg;

                                  2'b00,2'b11 : sum_reg <= p_reg;

                                endcase

                                iter_cnt <= iter_cnt + 1;

                      end

    SHIFT :  begin

                                p_reg <= {sum_reg[2*WIDTH+1],sum_reg[2*WIDTH+1:1]};

                       end

    OUTPUT: product =  p_reg>>1;

endcase

end//always ends

endmodule        //end of source code

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