ALU VLSI CODE

//ALU

module  alu(s,in1,in2,sel);

input [1:0] in1,in2;

input [3:0] sel;

reg [3:0] d;

output[8:0] s;

reg [8:0] s;

always

case(sel)

         4'b0000:d <= in1&in2;

                4'b0001:d <= in1|in2;

         4'b0010:d <= in1^in2;

                4'b0011:d <= {00,(~(in1^in2))};

                4'b0100:d <= in1-in2;

                4'b0101:d <= in1+in2;

         4'b0110:d <= in1*in2;

                4'b0111:d <= {00,(~(in1))};

                4'b1000:d <= {00,(~(in2))};

                4'b1001:d <= {00,(in1>>1)};

                4'b1010:d <= {00,(in1<<1)};

                4'b1011:d <= {00,(in2>>1)};

                4'b1100:d <= {00,(in2<<1)};

                4'b1101:d <= {00,~(in1&in2)};

                4'b1110:d <= {00,~(in1|in2)};

                4'b1111:d <= {in1,in2};

 endcase

 always

 case(d)

4'b0000: s <= 9'b000000011;

4'b0001: s <= 9'b010011111;

4'b0010: s <= 9'b000100101;

4'b0011: s <= 9'b000001101;

4'b0100: s <= 9'b010011001;

4'b0101: s <= 9'b001001001;

4'b0110: s <= 9'b001000001;

4'b0111: s <= 9'b000011111;

4'b1000: s <= 9'b000000001;

4'b1001: s <= 9'b000001001;

default: s <= 9'b000000000;

endcase

endmodule