This part briefs briefs about the different SFRs & its description and Instruction Set summary.
Special Function Registers
The 8051 operations that do not use the internal 128-byte RAM addresses from 00h to 7Fh are done by a group of specific internal registers, each called a special-function register (SFR), which may be addressed much like internal RAM, using addresses from 80h to FFh. This feature allows the programmer to change only what needs to be altered, leaving the remaining bits in that SFR unchanged. Not all of the addresses from 80h to FFh are used for SFRs, and attempting to use an address that is not defined, or "empty," results in unpredictable results. In Figure 2.1b, the SFR addresses are shown in the upper right corner of each block.
The SFR names and equivalent internal RAM addresses are given in the following table:
NAME
|
FUNCTION
|
ADDRESS (HEX)
|
A
|
Accumulator
|
0ED
|
B
|
Arithmetic
|
0F0
|
DPH
|
Addressing external memory
|
83
|
DPL
|
Addressing external memory
|
82
|
IE
|
Interrupt enable control
|
0A8
|
IP
|
Interrupt priority
|
0B8
|
P0
|
Input/output port latch
|
80
|
Pl
|
Input/output port latch
|
90
|
P2
|
Input/output port latch
|
AD0
|
P3
|
Input/output port latch
|
0B0
|
PC0N
|
Power control
|
87
|
PSW
|
Program status word
|
0DD
|
SCON
|
Serial port control
|
98
|
SBUF
|
Serial port data buffer
|
99
|
SP
|
Stack pointer
|
81
|
TMOD
|
Timer/counter mode control
|
89
|
TCON
|
Timer/counter control
|
88
|
TL0
|
Timer 0 low byte
|
8A
|
TH0
|
Timer 0 high byte
|
8e
|
TL1
|
Timer 1 low byte
|
88
|
TH1
|
Timer 1 high byte
|
8D
|
A and B Registers
The 8051 contains 34 general-purpose, or working, registers. Two of these, registers A and B, comprise the mathematical core of the 8051 central processing unit (CPU). The other 32 are arranged as part of internal RAM in four banks, B0-B3, of eight registers each, named R0 to R7.
The A (accumulator) register is the most versatile of the two CPU registers and is used for many operations, including addition, subtraction, integer multiplication and division, and Boolean bit manipulations. The A register is also used for all data transfers between the 8051 and any external memory. The B register is used with the A register for multiplication and division operations and has no other function other than as a location where data may be stored.
Flags and the Program Status Word (PSW)
Flags are 8-bit registers provided to store the results of certain program instructions. Other instructions can test the condition of the flags and make decisions based upon the flag states. In order that the flags may be conveniently addressed, they are grouped inside the program status word (PSW) and the power control (PCON) registers.
The 8051 has four math flags that respond automatically to the outcomes of math operations and three general-purpose user flags that can be set to I or cleared to 0 by the programmer as desired. The math flags include carry (C), auxiliary carry (AC), overflow (OY), and parity (P). User flags are named FO, GFO, and GFI; they are general-purpose flags that may be used by the programmer to record some event in the program.
7
|
6
|
5
|
4
|
3
|
2
|
1
|
0
|
CY
|
AC
|
F0
|
RS1
|
RS0
|
OV
|
P
|
Figure 1.4 – PSW register
RS1 RS0
|
Bank
|
Address
|
0 0
|
bank 0
|
00H-07H
|
0 1
|
bank 1
|
08H-0FH
|
1 0
|
bank 2
|
10H-17H
|
1 1
|
bank 3
|
18H-1FH
|
Note that all of the flags can be set and cleared by the programmer at will. The math flags, however, are also affected by math operations. The PSW contains the math flags, user program flag FO, and the register select bits that identify which of the four general purpose register banks is currently in use by the program. The remaining two user flags, GFO and GFI, are stored in PCON.
The Power Control SFR is used to control the 8051's power control modes. Certain operation modes of the 8051 allow the 8051 to go into a type of "sleep" mode which requires much less power. These modes of operation are controlled through PCON. Additionally, one of the bits in PCON is used to double the effective baud rate of the 8051's serial port.
7
|
6
|
5
|
4
|
3
|
2
|
1
|
0
|
SMOD
|
--
|
--
|
--
|
GF1
|
GF2
|
PD
|
IDL
|
TCON (Timer Control, Addresses 88h, Bit-Addressable):
The Timer Control SFR is used to configure and modify the way in which the 8051's two timers operate. This SFR controls whether each of the two timers is running or stopped and contains a flag to indicate that each timer has overflowed. Additionally, some non-timer related bits are located in the TCON SFR. These bits are used to configure the way in which the external interrupts are activated and also contain the external interrupt flags which are set when an external interrupt has occured.
7
|
6
|
5
|
4
|
3
|
2
|
1
|
0
|
TF1
|
TR1
|
TF0
|
TR0
|
IE1
|
IT1
|
IE0
|
IT0
|
• TF0/TF1: Timer0/1 overflow flag is set when the timer/ counter overflows, reset by program
• TR0/TR1: Timer0/1 run control bit is set to start, reset to stop the timer0/1
• IE0/IE1: External Interrupt 0/1 edge detected flag: 1 is set when a falling edge interrupt on the external port 0/1, reset(cleared) by hardware itself for falling edge transition-activated INT; Reset by code for low level INT.
• IT0/IT1 External Interrupt Type (1: falling edge triggered, 0 low level triggered)
TMOD (Timer Mode, Addresses 89h):
The Timer Mode SFR is used to configure the mode of operation of each of the two timers.
Timer1
|
Timer0
| ||||||
Gate
|
C/T
|
M1
|
M0
|
Gate
|
C/T
|
M1
|
M0
|
M1, M0 Mode Control
0 0 (Mode 0) 8 bit count mode
0 1 (Mode 1) 16 bit count mode
1 0 (Mode 2) Auto reload mode
1 1 (Mode 3) Multiple mode
TL0/TH0 (Timer 0 Low/High, Addresses 8Ah/8Ch):
These two SFRs, taken together, represent timer 0. Their exact behaviour depends on how the timer is configured in the TMOD SFR; however, these timers always count up. What is configurable is how and when they increment in value.
TL1/TH1 (Timer 1 Low/High, Addresses 8Bh/8Dh):
These two SFRs, taken together, represent timer 1. Their exact behaviour depends on how the timer is configured in the TMOD SFR; however, these timers always count up. What is configurable is how and when they increment in value.
P1 (Port 1, Address 90h, Bit-Addressable):
This is input/output port 1. Each bit of this SFR corresponds to one of the pins on the microcontroller. For example, bit 0 of port 1 is pin P1.0, bit 7 is pin P1.7. Writing a value of 1 to a bit of this SFR will send a high level on the corresponding I/O pin whereas a value of 0 will bring it to a low level.
SCON (Serial Control, Addresses 98h, Bit-Addressable):
The Serial Control SFR is used to configure the behavior of the 8051's on-board serial port. This SFR controls the baud rate of the serial port, whether the serial port is activated to receive data, and also contains flags that are set when a byte is successfully sent or received.
7
|
6
|
5
|
4
|
3
|
2
|
1
|
0
|
SM0
|
SM1
|
SM2
|
REN
|
TB8
|
RB8
|
TI
|
RI
|
SM0
|
SM1
|
Serial Mode
|
Baud Rate
|
Device
|
0
|
0
|
0 (Sync.)
half duplex,
|
Oscillator/12
(fixed)
|
8-bit shift register
|
0
|
1
|
1(Async)
full duplex
|
Set by Timer 1
|
8-bit UART
|
1
|
0
|
2(Sync)
half duplex
|
Oscillator/64
(fixed)
|
9-bit UART
|
1
|
1
|
3(Async)
full duplex
|
Set by Timer 1
|
9-bit UART
|
SBUF (Serial Control, Addresses 99h):
The Serial Buffer SFR is used to send and receive data via the on-board serial port. Any value written to SBUF will be sent out the serial port's TXD pin. Likewise, any value which the 8051 receives via the serial port's RXD pin will be delivered to the user program via SBUF. In other words, SBUF serves as the output port when written to and as an input port when read from.
P2 (Port 2, Address A0h, Bit-Addressable):
This is input/output port 2. Each bit of this SFR corresponds to one of the pins on the microcontroller. For example, bit 0 of port 2 is pin P2.0, bit 7 is pin P2.7. Writing a value of 1 to a bit of this SFR will send a high level on the corresponding I/O pin whereas a value of 0 will bring it to a low level.
IE (Interrupt Enable, Addresses A8h):
The Interrupt Enable SFR is used to enable and disable specific interrupts. The low 7 bits of the SFR are used to enable/disable the specific interrupts, where as the highest bit is used to enable or disable ALL interrupts. Thus, if the high bit of IE is 0 all interrupts are disabled regardless of whether an individual interrupt is enabled by setting a lower bit.
7
|
6
|
5
|
4
|
3
|
2
|
1
|
0
|
EA
|
-
|
ET2
|
ES
|
ET1
|
EX1
|
ET0
|
EX0
|
P3 (Port 3, Address B0h, Bit-Addressable):
This is input/output port 3. Each bit of this SFR corresponds to one of the pins on the microcontroller. For example, bit 0 of port 3 is pin P3.0, bit 7 is pin P3.7. Writing a value of 1 to a bit of this SFR will send a high level on the corresponding I/O pin whereas a value of 0 will bring it to a low level.
IP (Interrupt Priority, Addresses B8h, Bit-Addressable):
The Interrupt Priority SFR is used to specify the relative priority of each interrupt. On the 8051, an interrupt may either be of low (0) priority or high (1) priority. An interrupt may only interrupt interrupts of lower priority. For example, if we configure the 8051 so that all interrupts are of low priority except the serial interrupt, the serial interrupt will always be able to interrupt the system, even if another interrupt is currently executing. However, if a serial interrupt is executing no other interrupt will be able to interrupt the serial interrupt routine since the serial interrupt routine has the highest priority.
7
|
6
|
5
|
4
|
3
|
2
|
1
|
0
|
-
|
-
|
PT2
|
PS
|
PT1
|
PX1
|
PT0
|
PX0
|
8051 – Instruction Set
v Data Transfer
Move/Copy data from one location to another
¨ MOV, MOVC, MOVX, PUSH, POP, XCH, XCHD
v Logical
Perform logic operations on data
¨ ANL, ORL, XRL, CLR, CPL, RL, RLC, RR, RRC, SWAP
v Arithmetic
Perform arithmetic operations on data
¨ ADD, ADDC, SUBB, INC, DEC, MUL, DIV
v Program control
Control the program flow (jumps, subroutine calls)
¨ JMP, AJMP, LJMP, SJMP, JC, JNC, JB, JNB, JBC, JZ, JNZ, ACALL, LCALL, CJNE, DJNZ, RET, RETI
v NOP
|
Mnemonic
|
Description
|
Byte
|
Cycle
|
|
Data
Transfer Operations
|
|||
|
MOV A,Rn
|
Moves the register to the accumulator
|
1
|
1
|
|
MOV A,direct
|
Moves the direct byte to the
accumulator
|
2
|
2
|
|
MOV A,@Ri
|
Moves the indirect RAM to the
accumulator
|
1
|
2
|
|
MOV A,#data
|
Moves the immediate data to the
accumulator
|
2
|
2
|
|
MOV Rn,A
|
Moves the accumulator to the register
|
1
|
2
|
|
MOV Rn,direct
|
Moves the direct byte to the register
|
2
|
4
|
|
MOV Rn,#data
|
Moves the immediate data to the
register
|
2
|
2
|
|
MOV direct,A
|
Moves the accumulator to the direct
byte
|
2
|
3
|
|
MOV direct,Rn
|
Moves the register to the direct byte
|
2
|
3
|
|
MOV direct,direct
|
Moves the direct byte to the direct
byte
|
3
|
4
|
|
MOV direct,@Ri
|
Moves the indirect RAM to the direct
byte
|
2
|
4
|
|
MOV direct,#data
|
Moves the immediate data to the direct
byte
|
3
|
3
|
|
MOV @Ri,A
|
Moves the accumulator to the indirect
RAM
|
1
|
3
|
|
MOV @Ri,direct
|
Moves the direct byte to the indirect
RAM
|
2
|
5
|
|
MOV @Ri, #data
|
Moves the immediate data to the indirect
RAM
|
2
|
3
|
|
MOV DPTR, #data16
|
Loads the data pointer with a 16-bit
constant
|
3
|
3
|
|
MOVC A,@A + DPTR
|
Moves the code byte relative to the DPTR to
the accumulator
|
1
|
3
|
|
MOVC A,@A + PC
|
Moves the code byte relative to the PC to
the accumulator
|
1
|
3
|
|
MOVX A,@Ri
|
Moves the external RAM (eight-bit address)
to A
|
1
|
3-10
|
|
MOVX A,@DPTR
|
Moves the external RAM (16-bit address) to
A
|
1
|
3-10
|
|
MOVX @Ri,A
|
Moves A to the external RAM (eight-bit
address)
|
1
|
4-11
|
|
MOVX @DPTR,A
|
Moves A to the external RAM (16-bit
address)
|
1
|
4-11
|
|
PUSH direct
|
Pushes the direct byte onto the stack
|
2
|
4
|
|
POP direct
|
Pops the direct byte from the stack
|
2
|
3
|
|
XCH A,Rn
|
Exchanges the register with the
accumulator
|
1
|
2
|
|
XCH A,direct
|
Exchanges the direct byte with the
accumulator
|
2
|
3
|
|
XCH A,@Ri
|
Exchanges the indirect RAM with the
accumulator
|
1
|
3
|
|
XCHD A,@Ri
|
Exchanges the low-order nibble indirect
RAM with A
|
1
|
3
|
|
Logic
Operations
|
|||
|
ANL A,Rn
|
AND register to accumulator
|
1
|
1
|
|
ANL A,direct
|
AND direct byte to accumulator
|
2
|
2
|
|
ANL A,@Ri
|
AND indirect RAM to accumulator
|
1
|
2
|
|
ANL A,#data
|
AND immediate data to accumulator
|
2
|
2
|
|
ANL direct,A
|
AND accumulator to direct byte
|
2
|
3
|
|
ANL direct,#data
|
AND immediate data to direct byte
|
3
|
4
|
|
ORL A,Rn
|
OR register to accumulator
|
1
|
1
|
|
ORL A,direct
|
OR direct byte to accumulator
|
2
|
2
|
|
ORL A,@Ri
|
OR indirect RAM to accumulator
|
1
|
2
|
|
ORL A,#data
|
OR immediate data to accumulator
|
2
|
2
|
|
ORL direct,A
|
OR accumulator to direct byte
|
2
|
3
|
|
ORL direct,#data
|
OR immediate data to direct byte
|
3
|
4
|
|
XRL A,Rn
|
Exclusive OR register to accumulator
|
1
|
1
|
|
XRL A,direct
|
Exclusive OR direct byte to accumulator
|
2
|
2
|
|
XRL A,@Ri
|
Exclusive OR indirect RAM to
accumulator
|
1
|
2
|
|
XRL A,#data
|
Exclusive OR immediate data to
accumulator
|
2
|
2
|
|
XRL direct,A
|
Exclusive OR accumulator to direct byte
|
2
|
3
|
|
XRL direct,#data
|
Exclusive OR immediate data to direct
byte
|
3
|
4
|
|
CLR A
|
Clears the accumulator
|
1
|
1
|
|
CPL A
|
Complements the accumulator
|
1
|
1
|
|
RL A
|
Rotates the accumulator left
|
1
|
1
|
|
RLC A
|
Rotates the accumulator left through
carry
|
1
|
1
|
|
RR A
|
Rotates the accumulator right
|
1
|
1
|
|
RRC A
|
Rotates the accumulator right through
carry
|
1
|
1
|
|
SWAP A
|
Swaps nibbles within the accumulator
|
1
|
1
|
|
Boolean
Manipulation Operations
|
|||
|
CLR C
|
Clears the carry flag
|
1
|
1
|
|
CLR bit
|
Clears the direct bit
|
2
|
3
|
|
SETB C
|
Sets the carry flag
|
1
|
1
|
|
SETB bit
|
Sets the direct bit
|
2
|
3
|
|
CPL C
|
Complements the carry flag
|
1
|
1
|
|
CPL bit
|
Complements the direct bit
|
2
|
3
|
|
ANL C,bit
|
AND direct bit to the carry flag
|
2
|
2
|
|
ANL C,bit
|
AND complements of direct bit to the
carry
|
2
|
2
|
|
ORL C,bit
|
OR direct bit to the carry flag
|
2
|
2
|
|
ORL C,bit
|
OR complements of direct bit to the
carry
|
2
|
2
|
|
MOV C,bit
|
Moves the direct bit to the carry flag
|
2
|
2
|
|
MOV bit,C
|
Moves the carry flag to the direct bit
|
2
|
3
|
|
Arithmetic
Operations
|
|||
|
ADD A,@Ri
|
Adds the indirect RAM to the
accumulator
|
1
|
2
|
|
ADD A,#data
|
Adds the immediate data to the
accumulator
|
2
|
2
|
|
ADDC A,Rn
|
Adds the register to the accumulator
with a carry flag
|
1
|
1
|
|
ADDC A,direct
|
Adds the direct byte to A with a
carry flag
|
2
|
2
|
|
ADDC A,@Ri
|
Adds the indirect RAM to A with a
carry flag
|
1
|
2
|
|
ADDC A,#data
|
Adds the immediate data to A with
carry a flag
|
2
|
2
|
|
SUBB A,Rn
|
Subtracts the register from A with a
borrow
|
1
|
1
|
|
SUBB A,direct
|
Subtracts the direct byte from A with
a borrow
|
2
|
2
|
|
SUBB A,@Ri
|
Subtracts the indirect RAM from A
with a borrow
|
1
|
2
|
|
SUBB A,#data
|
Subtracts the immediate data from A
with a borrow
|
2
|
2
|
|
INC A
|
Increments the accumulator
|
1
|
1
|
|
INC Rn
|
Increments the register
|
1
|
2
|
|
INC direct
|
Increments the direct byte
|
2
|
3
|
|
INC @Ri
|
Increments the indirect RAM
|
1
|
3
|
|
DEC A
|
Decrements the accumulator
|
1
|
1
|
|
DEC Rn
|
Decrements the register
|
1
|
1
|
|
DEC direct
|
Decrements the direct byte
|
1
|
2
|
|
DEC @Ri
|
Decrements the indirect RAM
|
2
|
3
|
|
INC DPTR
|
Increments the data pointer
|
1
|
3
|
|
MUL A,B
|
Multiplies A and B
|
1
|
5
|
|
DIV A,B
|
Divides A by B
|
1
|
5
|
|
DA A
|
Decimal adjust accumulator
|
1
|
1
|
|
Program
Branch Operations
|
|||
|
ACALL addr11
|
Absolute subroutine call
|
2
|
6
|
|
LCALL addr16
|
Long subroutine call
|
3
|
6
|
|
RET Return
|
Return from subroutine
|
1
|
4
|
|
RETI Return
|
Return from interrupt
|
1
|
4
|
|
AJMP addr11
|
Absolute jump
|
2
|
3
|
|
LJMP addr16
|
Long jump
|
3
|
4
|
|
SJMP rel
|
Short jump (relative address)
|
2
|
3
|
|
JMP @A + DPTR
|
Jump indirect relative to the DPTR
|
1
|
2
|
|
JZ rel
|
Jump if accumulator is zero
|
2
|
3
|
|
JNZ rel
|
Jump if accumulator is not zero
|
2
|
3
|
|
JC rel
|
Jump if carry flag is set
|
2
|
3
|
|
JNC rel
|
Jump if carry flag is not set
|
2
|
3
|
|
JB bit,rel
|
Jump if direct bit is set
|
3
|
4
|
|
JNB bit,rel
|
Jump if direct bit is not set
|
3
|
4
|
|
JBC bit,rel
|
Jump if direct bit is set and clears
bit
|
3
|
4
|
|
CJNE A,direct,rel
|
Compares direct byte to A and
jumps if not equal
|
3
|
4
|
|
CJNE A,#data,rel
|
Compares immediate to A and
jumps if notequal
|
3
|
4
|
|
CJNE Rn,#data rel
|
Compares immediate to the register
and
jumps if not equal
|
3
|
4
|
|
CJNE @Ri,#data,rel
|
Compares immediate to indirect and
jumps if not equal
|
3
|
4
|
|
DJNZ Rn,rel
|
Decrements register and jumps if not
zero
|
2
|
3
|
|
DJNZ direct,rel
|
Decrements direct byte and jumps if
not zero
|
3
|
4
|
|
NOP
|
No operation
|
1
|
1
|
Viewers comments
are encouraged.
This helps us to much
more.
Thank you!!!
0 comments:
Post a Comment