Friday, 21 March 2014

VLSI - SYNCHRONOUS DUAL PORT RAM VERILOG VHDL CODE

By  at Friday, March 21, 2014  , , , ,  3 comments

    Here is the code for Dual Port RAM in Verilog & VHDL. This is designed as Dual port write only-read only type.
    The PortA is used for writing data alone to RAM while PortB is used for reading only.

    This will be helpful for image processing applications, where the Control Unit will provide data for Processing Unit.

Block Diagram:
clk         - Clock
addra   - P.A address (4 bit)
addrb   - P.B address(4 bit)
dina      - P.A input data (8 bit)
doutb  - P.A input data (8 bit)
ena     - Enable P.A operations
wea    - Enable P.A Write operation
enb     - Enable P.B operations
DUAL PORT RAM VERILOG CODE:
// // // // // // // // // // // // // // // // // // // // // // //
// Author: ElecDude
//         admin@elecdude.com      
//
// Copyright - 2014 - ElecDude
//
// DISCLAIMER:
//
// THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT       
// RESTRICTION PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT  
// REMOVED FROM THE FILE AND THAT ANY DERIVATIVE WORK CONTAINS
// THE ORIGINAL COPYRIGHT NOTICE AND THE ASSOCIATED DISCLAIMER.
// 
// This is provided without any express or implied warranties,
// including, but not limited to, the implied warranties of merchantability
// and fitnessfor a particular purpose. FOR EDUCATIONAL PURPOSE ONLY.
//
// // // // // // // // // // // // // // // // // // // // // // //
module dpram(dina, dinb,addra, addrb,ena, wrb_a, enb, wrb_b, clk,douta, doutb);
//Definitions
      parameter ADDR_WIDTH = 4; //memory size address width
      parameter DATA_WIDTH = 8; //data bus width
      parameter RAM_DEPTH = 1 << ADDR_WIDTH;
//Input & Output Ports
      input [DATA_WIDTH-1:0] dina, dinb;
      input [ADDR_WIDTH-1:0] addra, addrb;
      input ena, wrb_a, enb, wrb_b, clk;
      output reg [7:0] douta, doutb;
// Declare the mem variable
      reg [7:0] mem[0:RAM_DEPTH-1];
     
// Port A
always @ (posedge clk)  begin
if (ena && wrb_a)  begin
      mem[addra] <= dina;
      douta <= dina;
 end
else if(ena && (!wrb_a)) begin
      douta <= mem[addra];
 end
end
     
// Port B
always @ (posedge clk)  begin
if (enb && wrb_b) begin
      mem[addrb] <= dinb;
      doutb <= dinb;
 end
else if(enb && (!wrb_b)) begin
      doutb <= mem[addrb];
 end
end
     
endmodule


DUAL PORT RAM VHDL CODE:
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --  
-- Author: ElecDude
--         admin@elecdude.com      
--
-- Copyright - 2014 - ElecDude
--
-- DISCLAIMER:
--
-- THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT       
-- RESTRICTION PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT  
-- REMOVED FROM THE FILE AND THAT ANY DERIVATIVE WORK CONTAINS
-- THE ORIGINAL COPYRIGHT NOTICE AND THE ASSOCIATED DISCLAIMER.
-- 
-- This is provided without any  express or implied warranties,
-- including, but not limited  to, the implied warranties of merchantability
-- and fitnessfor a particular purpose. FOR EDUCATIONAL PURPOSE ONLY.
--
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

ENTITY dpram is
      GENERIC
      (
            ADRESS_WIDTH: integer := 4;  
            DATA_WIDTH  : integer := 8
      );
      PORT
      (     clk   : in std_logic;
            ena,wea,enb : in std_logic;
            addra,addrb : in std_logic_vector(ADRESS_WIDTH-1 downto 0);
            dina  : in std_logic_vector(DATA_WIDTH-1 downto 0);
            doutb : out std_logic_vector(DATA_WIDTH-1 downto 0)
      );
END dpram;

ARCHITECTURE Behavioral OF dpram IS
constant RAM_SIZE :integer := 2**ADRESS_WIDTH;
TYPE mem_array IS ARRAY (0 TO RAM_SIZE-1) OF std_logic_vector(DATA_WIDTH-1 DOWNTO 0);
signal ram : mem_array;
begin
--conv_std_logic_vector(x,m)
process(clk)
begin
      IF(clk'EVENT AND clk='1') THEN
            IF(ena='1' AND wea='1') THEN
                  ram(conv_integer(addra)) <= dina;
            END IF;
      END IF;
end process;

process(clk)
begin
      IF(clk'EVENT AND clk='1') THEN
            IF(enb='1') THEN
                  doutb <= ram(conv_integer(addrb));
            END IF;
      END IF;
end process;

END Behavioral;



MODELSIM SIMULATION TRANSCRIPT
vlib work
vlog  +acc  "dpram.v"
#vcom +acc  "dpram2.vhd"
vsim -t 1ns  -novopt -lib work dpram
view wave
add wave *
add wave \
{sim:/dpram/mem }
view structure
view signals
run 10ns
force -freeze sim:/dpram/clk 1 15, 0 {65 ns} -r 100
force -freeze sim:/dpram/ena 0 0
force -freeze sim:/dpram/wrb_a 0 0
force -freeze sim:/dpram/wrb_b 0 0
force -freeze sim:/dpram/enb 0 0
force -freeze sim:/dpram/dina 00000000 0
force -freeze sim:/dpram/dinb 00000000 0
force -freeze sim:/dpram/addra 0000 0
force -freeze sim:/dpram/addrb 0000 0
run
force -freeze sim:/dpram/ena 1 0
force -freeze sim:/dpram/wrb_a 1 0
force -freeze sim:/dpram/addra 0000 0
force -freeze sim:/dpram/dina 00000001 0
run
force -freeze sim:/dpram/addra 0001 0
force -freeze sim:/dpram/dina 00000011 0
run
force -freeze sim:/dpram/addra 0010 0
force -freeze sim:/dpram/dina 00000111 0
run
force -freeze sim:/dpram/addra 0011 0
force -freeze sim:/dpram/dina 00001111 0
run
force -freeze sim:/dpram/addra 0100 0
force -freeze sim:/dpram/dina 00011111 0
run
force -freeze sim:/dpram/addra 0101 0
force -freeze sim:/dpram/dina 00011111 0
run
force -freeze sim:/dpram/addra 0110 0
force -freeze sim:/dpram/dina 0101011 0
run
force -freeze sim:/dpram/addra 0111 0
force -freeze sim:/dpram/dina 01110011 0
run
force -freeze sim:/dpram/addra 1000 0
force -freeze sim:/dpram/dina 00111111 0
run
force -freeze sim:/dpram/addra 1001 0
force -freeze sim:/dpram/dina 01111111 0
run
force -freeze sim:/dpram/ena 0 0
force -freeze sim:/dpram/wrb_a 0 0
run
force -freeze sim:/dpram/enb 1 0
force -freeze sim:/dpram/addrb 0000 0
run
force -freeze sim:/dpram/addrb 0010 0
run
force -freeze sim:/dpram/addrb 0100 0
run
force -freeze sim:/dpram/addrb 0110 0
run
force -freeze sim:/dpram/addrb 1000 0
run
force -freeze sim:/dpram/addrb 0010 0
run
force -freeze sim:/dpram/addrb 0110 0
run
force -freeze sim:/dpram/addrb 1000 0
run
force -freeze sim:/dpram/enb 0 0
run
run



SIMULATION WAVEFORM:


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