Sunday, 16 March 2014

VLSI - Universal Shift register in Verilog Code


          Here is the code fo Universal Shift register in Verilog. This is a parallel shift register. It can shift left & right controlled by "lrb".


         It simultaneously shifts data out from lsb & sotres input data from din to lsb, if lrb=1 which is shift left. And vice versa for right shift.
         If load signal is '0', datain is loaded into shift register.
         Once the rd signal is asserted, the shift register contents are loaded into dataout.
         Data from shift register is shifted out at every negative edge of CLK, if en is '1'.

This code has synthesized in Xilinx ISE for Spartan 3E and clock frequency is more than 400MHz.

/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* Company: elecdude.com   
* Engineer: sa
*
* Design Name:
* Module Name:  Universla Shiftreg
*
* Author: ElecDude
*         admin@elecdude.com                               
*
* Copyright - 2014 - ElecDude
*
* THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT       
* RESTRICTION PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT  
* REMOVED FROM THE FILE AND THAT ANY DERIVATIVE WORK CONTAINS
* THE ORIGINAL COPYRIGHT NOTICE AND THE ASSOCIATED DISCLAIMER.

* This is provided without any  express or implied warranties,
* including, but not limited  to, the implied warranties of merchantability
* and fitnessfor a particular purpose. FOR EDUCATIONAL PURPOSE ONLY.
*
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */

module shiftreg(clk,en,rd,load,lrb,rstb, datin, tdat, datout, rdat);
    input clk,en,lrb,rstb,rd,load;
    input datin;
    input [7:0] tdat;
    output reg datout;
    output reg [7:0] rdat;
    reg [7:0] sr;

always @(rstb or rd) begin
 if(rstb==0) begin
    rdat<=0;
 end
 else
    if(rd==1) rdat<=sr;
 end

always @(negedge rstb or negedge clk) begin
 if(rstb==0) begin
    sr<=0; datout<=0;
 end
 else begin
    if(load==1) begin  //load=1 if(nbit==0)
        if(lrb==0) // 0-> right shift
            {sr,datout} <= {datin,tdat};
        else // 1-> left shift
            {datout,sr} <= {tdat,datin};
        end
    else begin
        if(en==0) begin //en=ss, skips 1st edge 
            if(lrb==0)
                {sr,datout} <= {datin,sr};
            else
                {datout,sr} <= {sr,datin};
            end
        end
 end
end //always ends

endmodule
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