Sunday, 23 March 2014

VHDL - JOHNSON & RING COUNTER CODE - VLSI LAB

VHDL - JOHNSON & RING COUNTER CODE -
VLSI LAB MANUAL


Here is the code for  Johnson & Ring Counter in VHDL. This is the synthesised code in Xilinx ISE.

The working is simple..
reset, clk are the inputs
x is data out
if reset is '1', then all register are loaded all zeros
else for every rising clock edge, the count is advanced.

Johnson counter

-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Company: elecdude.com
-- Engineer: sa
--
-- Create Date:    16:44:55 03/12/2014
-- Design Name: JohnsonCounter
-- Module Name:  john
--
-- Author: ElecDude
--         admin@elecdude.com         
--
-- Copyright - 2014 - ElecDude
--
-- DISCLAIMER:
--
-- THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT       
-- RESTRICTION PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT  
-- REMOVED FROM THE FILE AND THAT ANY DERIVATIVE WORK CONTAINS
-- THE ORIGINAL COPYRIGHT NOTICE AND THE ASSOCIATED DISCLAIMER.
-- 
-- This is provided without any  express or implied warranties,
-- including, but not limited  to, the implied warranties of merchantability
-- and fitnessfor a particular purpose. FOR EDUCATIONAL PURPOSE ONLY.
--
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity john is
    Port ( clk,rst : in  STD_LOGIC;
           x : out  STD_LOGIC_VECTOR (3 downto 0));
end john;

architecture Behavioral of john is
signal r_reg,r_next:std_logic_vector(3 downto 0);
begin
process(clk,rst)
begin
if(rst='1')then
r_reg<=(0=>'1',others=>'0');
elsif(clk'event and clk='1')then
r_reg<=r_next;
end if;
end process;
r_next<=(not r_reg(0))&r_reg(3 downto 1);
x<=r_reg;
end Behavioral;

Truth Table

RST
CLK
X
1
x
0000
0
0 -> 1
0000
0
0 -> 1
1000
0
0 -> 1
1100
0
0 -> 1
1110
0
0 -> 1
1111
0
0 -> 1
0111
0
0 -> 1
0011
0
0 -> 1
0001
0
0 -> 1
0000

Ring counter

-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Company: elecdude.com
-- Module Name:   Ring - Behavioral
-- Author: ElecDude
--         admin@elecdude.com         
-- Copyright - 2014 - ElecDude
--
-- DISCLAIMER:
-- THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT       
-- RESTRICTION PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT  
-- REMOVED FROM THE FILE AND THAT ANY DERIVATIVE WORK CONTAINS
-- THE ORIGINAL COPYRIGHT NOTICE AND THE ASSOCIATED DISCLAIMER.
-- 
-- This is provided without any  express or implied warranties,
-- including, but not limited  to, the implied warranties of merchantability
-- and fitnessfor a particular purpose. FOR EDUCATIONAL PURPOSE ONLY.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity ringc is
    Port ( clk,rst : in  STD_LOGIC;
           x : out  STD_LOGIC_VECTOR (3 downto 0));
end ringc;

architecture Behavioral of ringc is
signal r_reg:std_logic_vector(3 downto 0);
begin
process(clk,rst)
begin
if(rst='1')then
  r_reg<=(3=>'1',others=>'0');
elsif(clk'event and clk='1')then
  r_reg(3)<=r_reg(2);
  r_reg(2)<=r_reg(1);
  r_reg(1)<=r_reg(0);
  r_reg(0)<=r_reg(3);
end if;
end process;
x<=r_reg;
end Behavioral;

Truth Table

rst
clk
out
1
x
1000
0
0 -> 1
0001
0
0 -> 1
0010
0
0 -> 1
0100
0
0 -> 1
1000
0
0 -> 1
0001
0
0 -> 1
0010





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