Saturday, 15 March 2014

VHDL - ASYNCHRONOUS & SYNCHRONOUS UP DOWN COUNTER CODE - VLSI LAB

VHDL - ASYNCHRONOUS & SYNCHRONOUS UP DOWN COUNTER CODE -
VLSI LAB MANUAL


Here is the code for  Asynchronous & Synchronous Up-Down Counter in VHDL. This is the synthesised code in Xilinx ISE.

The working is simple..
reset, clk & udb  are the inputs
c_out is serial data out
if reset is '0', then count value & cout is loaded all zeros
     Synchronously for SYNCCOUNTER (dependent on clock)
     Asynchronously for ASYNC_COUNTER (idependent on clock)
else for every rising clock edge, count value is incremented if (udb=1) else decrement if(udb=0) &  loaded into cout.

Synchronous Up Down counter

-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Company: elecdude.com
-- Engineer: sa
--
-- Create Date:    16:44:55 03/12/2014
-- Design Name: Synchronous Counter
-- Module Name:    syn_udcount - Behavioral
--
-- Author: ElecDude
--         admin@elecdude.com         
--
-- Copyright - 2014 - ElecDude
--
-- DISCLAIMER:
--
-- THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT       
-- RESTRICTION PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT  
-- REMOVED FROM THE FILE AND THAT ANY DERIVATIVE WORK CONTAINS
-- THE ORIGINAL COPYRIGHT NOTICE AND THE ASSOCIATED DISCLAIMER.
-- 
-- This is provided without any  express or implied warranties,
-- including, but not limited  to, the implied warranties of merchantability
-- and fitnessfor a particular purpose. FOR EDUCATIONAL PURPOSE ONLY.
--
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity syn_udcount is
    Port ( clk,rstb,u_db : in  STD_LOGIC;
           c_out : out  STD_LOGIC_VECTOR (3 downto 0));
end syn_udcount;

architecture Behavioral of syn_udcount is
SIGNAL cvalue:STD_LOGIC_VECTOR (3 downto 0); -- temporary count registr
begin

PROCESS (clk,rstb) IS BEGIN
IF (clk'EVENT AND clk='1') THEN --rising edge
 IF rstb='0' THEN --synchronous reset
    cvalue <= "0000";
 ELSE
    IF u_db ='1' THEN
        cvalue<=cvalue+1; --count up
    ELSE
        cvalue<=cvalue-1; --count down
    END IF;
 END IF;
END IF;
end process;

c_out<=cvalue; --put count value to output

end Behavioral;

Asynchronous Up Down counter

-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Company: elecdude.com
-- Module Name:    asyn_udcount - Behavioral
-- Author: ElecDude
--         admin@elecdude.com         
-- Copyright - 2014 - ElecDude
--
-- DISCLAIMER:
-- THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT       
-- RESTRICTION PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT  
-- REMOVED FROM THE FILE AND THAT ANY DERIVATIVE WORK CONTAINS
-- THE ORIGINAL COPYRIGHT NOTICE AND THE ASSOCIATED DISCLAIMER.
-- 
-- This is provided without any  express or implied warranties,
-- including, but not limited  to, the implied warranties of merchantability
-- and fitnessfor a particular purpose. FOR EDUCATIONAL PURPOSE ONLY.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity asyn_udcount is
    Port ( clk,rstb,u_db : in  STD_LOGIC;
           c_out : out  STD_LOGIC_VECTOR (3 downto 0));
end asyn_udcount;

architecture Behavioral of asyn_udcount is
SIGNAL cvalue:STD_LOGIC_VECTOR (3 downto 0);
begin

PROCESS (clk,rstb) IS BEGIN
 IF rstb='0' THEN --asynchronous reset
    cvalue <= "0000";
 ELSIF (clk'EVENT AND clk='1') THEN --rising edge
    IF u_db ='1' THEN
        cvalue<=cvalue+1;
    ELSE
        cvalue<=cvalue-1;
    END IF;
 END IF;
end process;

c_out<=cvalue;

end Behavioral;

MODELSIM SIMULATION COMMAND

view wave
add wave *
view structure
view signals
run 2ns
force -freeze sim:/
asyn_udcountua/rstb 0 0
force -freeze sim:/
asyn_udcountua/u_db 1 0
run 1ns
force -freeze sim:/
asyn_udcount/clk 1 20, 0 {520 ps} -r 1000
run 1ns
force -freeze sim:/
asyn_count/rstb 1 0
run 7ns
force -freeze sim:/
asyn_count/u_db 0 0
run 3ns

 Output Waveform:




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