Tuesday, 18 March 2014

VHDL - SHIFT REGISTER CODE - VLSI LAB

VHDL - SHIFT REGISTER CODE - VLSI LAB MANUAL

Here is the code for Shift register in VHDL. This is the synthesised code in Xilinx ISE.

The working is simple..
reset, clk, load are the inputs
datain is parallel data in
dout is serial data out
if reset is '0', then shiftregister & dout is loaded all zeros
if load signal is 1, then input data is loaded into shift register else the data in it right shifted out every rising of clock.
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Company: elecdude.com
-- Engineer: sa
--
-- Create Date:    12:36:23 03/12/2014
-- Design Name:
-- Module Name:    shiftreg - Behavioral
--
-- Author: ElecDude
--         admin@elecdude.com         
--
-- Copyright - 2014 - ElecDude
--
-- DISCLAIMER:
--
-- THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT       
-- RESTRICTION PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT  
-- REMOVED FROM THE FILE AND THAT ANY DERIVATIVE WORK CONTAINS
-- THE ORIGINAL COPYRIGHT NOTICE AND THE ASSOCIATED DISCLAIMER.
-- 
-- This is provided without any  express or implied warranties,
-- including, but not limited  to, the implied warranties of merchantability
-- and fitnessfor a particular purpose. FOR EDUCATIONAL PURPOSE ONLY.
--
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity shiftreg is
    Port ( reset,clk,load_shiftbar : in  STD_LOGIC;
           datain : in  STD_LOGIC_VECTOR (7 downto 0);
           dout : out  STD_LOGIC);
end shiftreg;

architecture Behavioral of shiftreg is
SIGNAL sr:STD_LOGIC_VECTOR (7 downto 0);

begin
PROCESS (clk,reset) IS
BEGIN
IF reset='0' THEN
    sr <= "00000000";
    dout<='0';
ELSIF (clk'EVENT AND clk='1') THEN
        IF load_shiftbar ='1' THEN --load input data into ShiftRegister
            sr<=datain;
        ELSE --start shifting out (shift right)
            sr(7)<='1';
            sr(6)<=sr(7);
            sr(5)<=sr(6);
            sr(4)<=sr(5);
            sr(3)<=sr(4);
            sr(2)<=sr(3);
            sr(1)<=sr(2);
            sr(0)<=sr(1);
            dout<=sr(0);
        END IF;
END IF;
END PROCESS;
end Behavioral;


Output Waveform:





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