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Friday, 15 June 2012

TRAFFIC LIGHT CONTROLLER VLSI CODE



//TRAFFIC LIGHT CONTROLLER
module tlc(N,E,W,S,clk);

output [2:0] N,E,W,S;
input clk;
parameter s0=3'b000;
parameter s1=3'b001;
parameter s2=3'b010;
parameter s3=3'b011;
parameter s4=3'b100;
parameter s5=3'b101;
parameter s6=3'b110;
parameter s7=3'b111;

parameter R=3'b001;
parameter Y=3'b010;
parameter G=3'b100;

reg [2:0] N,E,W,S;
reg [2:0] state;
integer t=0;

initial    //initialize
 begin
      state <= s0;
      t <= 0;
 end

//--------------TIMING CONTROL-----------
always@(posedge clk)
 begin
//  next_state=state;
  case(state)
   s0:if(t==20) //N=G
         begin
            state=s1;
              t=0;
         end
      else
         t=t+1;
   s1:if(t==5)       //N=Y
         begin
            state=s2;
              t=0;
         end
      else
         t=t+1;
     s2:if(t==20)    //E=G
         begin
            state=s3;
              t=0;
         end
      else
         t=t+1;

   s3:if(t==5)       //E=Y
         begin
            state=s4;
              t=0;
         end
      else
         t=t+1;
               
     s4:if(t==20)    //S=G
         begin
            state=s5;
              t=0;
         end
      else
         t=t+1;

   s5:if(t==5)       //S=Y
         begin
            state=s6;
              t=0;
         end
      else
         t=t+1;
               
     s6:if(t==20)    //W=G
         begin
            state=s7;
              t=0;
         end
      else
         t=t+1;

   s7:if(t==5)       //W=Y
         begin
            state=s0;
              t=0;
         end
      else
         t=t+1;
   default: state=s0;
  endcase
 end  //end of always block

//--------------LIGHT CONTROL-----------
 always @ (state)
  begin
      case (state)
         s0:{N,E,W,S}={G,R,R,R};
            s1:{N,E,W,S}={Y,R,R,R};
            
            s2:{N,E,W,S}={R,G,R,R};
            s3:{N,E,W,S}={R,Y,R,R};
          

            s4:{N,E,W,S}={R,R,G,R};
            s5:{N,E,W,S}={R,R,Y,R};
           
            s6:{N,E,W,S}={R,R,R,G};
            s7:{N,E,W,S}={R,R,R,Y};
            default:{N,E,W,S}={G,R,R,R};
      endcase
  end

endmodule


Thursday, 14 June 2012

ALU VLSI CODE



//ALU
module  alu(s,in1,in2,sel);
input [1:0] in1,in2;
input [3:0] sel;
reg [3:0] d;
output[8:0] s;
reg [8:0] s;
always
case(sel)
         4'b0000:d <= in1&in2;
                4'b0001:d <= in1|in2;
         4'b0010:d <= in1^in2;
                4'b0011:d <= {00,(~(in1^in2))};
                4'b0100:d <= in1-in2;
                4'b0101:d <= in1+in2;
         4'b0110:d <= in1*in2;
                4'b0111:d <= {00,(~(in1))};
                4'b1000:d <= {00,(~(in2))};
                4'b1001:d <= {00,(in1>>1)};
                4'b1010:d <= {00,(in1<<1)};
                4'b1011:d <= {00,(in2>>1)};
                4'b1100:d <= {00,(in2<<1)};
                4'b1101:d <= {00,~(in1&in2)};
                4'b1110:d <= {00,~(in1|in2)};
                4'b1111:d <= {in1,in2};
 endcase
 always
 case(d)
4'b0000: s <= 9'b000000011;
4'b0001: s <= 9'b010011111;
4'b0010: s <= 9'b000100101;
4'b0011: s <= 9'b000001101;
4'b0100: s <= 9'b010011001;
4'b0101: s <= 9'b001001001;
4'b0110: s <= 9'b001000001;
4'b0111: s <= 9'b000011111;
4'b1000: s <= 9'b000000001;
4'b1001: s <= 9'b000001001;
default: s <= 9'b000000000;
endcase
endmodule


7 SEGMENT VLSI CODE



//7 SEG
module segx(s,d);
input [2:0] d;
output[8:0] s;
reg [8:0] s;
always @(d)
   case(d)
3'b000: s <= 9'b000000011;
3'b001: s <= 9'b010011111;
3'b010: s <= 9'b000100101;
3'b011: s <= 9'b000001101;
3'b100: s <= 9'b010011001;
3'b101: s <= 9'b001001001;
3'b110: s <= 9'b001000001;
3'b111: s <= 9'b000011111;
   endcase
endmodule

Wednesday, 13 June 2012

IIR FILTER


//IIR FILTER
module IIR_Filter_8 (Data_out, Data_in, clock, reset);
                parameter          order = 8;
                parameter          word_size_in = 8;                                                                            
                parameter          word_size_out = 2*word_size_in + 2;
                output                  [word_size_out -1: 0] Data_out;
                input                     [word_size_in-1: 0] Data_in;
                input                     clock, reset;
               
                parameter          b0 = 8’d7;            // Feedforward filter coefficients
                parameter          b1 = 8’d17;
                parameter          b2 = 8’d32;
                parameter          b3 = 8’d46;
                parameter          b4 = 8’d52;
                parameter          b5 = 8’d46;
                parameter          b6 = 8’d32;
                parameter          b7 = 8’d17;
                parameter          b8 = 8’d7;
               
                parameter          a1 = 8’d46;          // Feedback filter coefficients
                parameter          a2 = 8’d32;
                parameter          a3 = 8’d17;
                parameter          a4 = 8’d0;
                parameter          a5 = 8’d17;
                parameter          a6 = 8’d32;
                parameter          a7 = 8’d46;
                parameter          a8 = 8’d52;
               
                reg         [word_size_in-1 : 0]        Samples_in [0: order];
                reg         [word_size_in-1 : 0]        Samples_out [1: order];
                wire       [word_size_out-1 : 0]    Data_feedforward;
                wire       [word_size_out-1 : 0]    Data_feedback;
                integer k;
            assign Data_feedforward =  b0 * Samples_in[0]
                                                                + b1 * Samples_in[1]
                                                                + b2 * Samples_in[2]
                                                                + b3 * Samples_in[3]
                                                                + b4 * Samples_in[4]
                                                                + b5 * Samples_in[5]
                                                                + b6 * Samples_in[6]
                                                                + b7 * Samples_in[7]
                                                                + b8 * Samples_in[8];
           assign Data_feedback = a1 * Samples_out [1]
                                                                + a2 * Samples_out [2]
                                                                + a3 * Samples_out [3]
                                                                + a4 * Samples_out [4]
                                                                + a5 * Samples_out [5]
                                                                + a6 * Samples_out [6]
                                                                + a7 * Samples_out [7]
                                                                + a8 * Samples_out [8];
         assign Data_out = Data_feedforward + Data_feedback;
always @ (posedge clock)
                 if (reset == 1)
                                begin
                                                Samples_in [0] <= 0;                      
                                                for (k = 1; k <= order; k = k+1)
                                                                begin
                                                                                Samples_in [k] <= 0;
                                                                                Samples_out [k] <= 0;
                                                                end
                                end
                 else
                                begin
                                                Samples_in [0]  <= Data_in;
                                                Samples_in [1]  <= Samples_in [0] ;
                                                Samples_out [1] <= Data_out;
                                               
                                                for (k = 2; k <= order; k = k+1)
                                                                begin
                                                                                Samples_in [k] <= Samples_in [k-1];                                                                                       Samples_out [k] <= Samples_out [k-1];
                                                                end
                      end
endmodule



BOOTH MULTIPLIER VLSI CODE


//BOOTH MULTIPLIER
module booth #(parameter WIDTH=4)
 (  input     clk,
    input     enable,
    input    [WIDTH-1:0] multiplier,                           
    input    [WIDTH-1:0] multiplicand,
   output reg [2*WIDTH-1:0] product);

parameter          IDLE       = 2'b00,                                // state encodings
ADD   = 2'b01,
                SHIFT     = 2'b10,
                OUTPUT = 2'b11;

reg  [1:0]              current_state, next_state;  // state registers.
reg  [2*WIDTH+1:0] a_reg,s_reg,p_reg,sum_reg;  // computational values.
reg  [WIDTH-1:0]      iter_cnt;          // iteration count for determining when done.
wire [WIDTH:0]                    multiplier_neg;  // negative value of multiplier

always @(posedge clk)
  if (!enable) current_state = IDLE;
  else         current_state = next_state;

always @* begin
next_state = 2'bx;
case (current_state)
   IDLE: if (enable)  next_state = ADD;
            else  next_state = IDLE;
   ADD:  next_state = SHIFT;
   SHIFT: if (iter_cnt==WIDTH) next_state = OUTPUT;
              else   next_state = ADD;
   OUTPUT:  next_state = IDLE;
endcase
end
// negative value of multiplier.
assign multiplier_neg = -{multiplier[WIDTH-1],multiplier};

// algorithm implemenation details.
always @(posedge clk) begin
  case (current_state)
    IDLE :  begin
                        a_reg    <= {multiplier[WIDTH-1],multiplier,{(WIDTH+1){1'b0}}};
                        s_reg    <= {multiplier_neg,{(WIDTH+1){1'b0}}};
                        p_reg    <= {{(WIDTH+1){1'b0}},multiplicand,1'b0};
                        iter_cnt <= 0;
                     end
    ADD  :  begin
                                case (p_reg[1:0])
                                  2'b01       : sum_reg <= p_reg+a_reg;
                                  2'b10       : sum_reg <= p_reg+s_reg;
                                  2'b00,2'b11 : sum_reg <= p_reg;
                                endcase
                                iter_cnt <= iter_cnt + 1;
                      end
    SHIFT :  begin
                                p_reg <= {sum_reg[2*WIDTH+1],sum_reg[2*WIDTH+1:1]};
                       end
    OUTPUT: product =  p_reg>>1;
endcase
end//always ends

endmodule        //end of source code


BCD TO SEVEN SEGMENT DISPLAY EMBEDDED C




BCD TO SEVEN SEGMENT DISPLAY




THEORY:
     A 7-segment display is a form of electronic display device for displaying decimal numerals that is an alternative to the more complex dot-matrix displays. Seven-segment displays are widely used in digital clocks, electronic meters, and other electronic devices for displaying numerical information.
The seven segments are arranged as a rectangle of two vertical segments on each side with one horizontal segment on the top, middle, and bottom. The segments of a 7-segment display are referred to by the letters A to G, where the optional DP decimal point (an "eighth segment") is used for the display of non-integer numbers.


BCD I/P
SEGMENT O/P
DISPLAY
g f e d c b a
0   0   0   0
0 1 1 1 1 1 1
0
0   0   0   1
0 0 0 0 1 1 0
1
0   0   1   0
1 0 1 1 0 1 1
2
0   0   1   1
1 0 0 1 1 1 1
3
0   1   0   0
0 1 1 0 0 1 1
4
0   1   0   1
1 1 0 1 1 0 1
5
0   1   1   0
0 0 1 1 1 1 1
6
0   1   1   1
0 0 0 0 1 1 1
7
1   0   0   0
1 1 1 1 1 1 1
8
1   0   0   1
1 1 0 0 1 1 1
9

CIRCUIT SCHEMATIC & OUTPUT:

PERIPHERAL OUTPUT:
SOURCE CODE:

#include<regx51.h>
sfr out=0xA0; //P3
sfr inp=0x90; //P1
unsigned char temp;
unsigned char const lookup[10]=
           {0xC0,0xF9,0xA4,0xB0,0x99,0x92,0x82,0xF8,0x80,0x90};

void main()
{
out=0x00;
inp=0xFF;
while(1)
  {
     temp=inp & 0x0F;
     if(temp>=0x0A)
          out=0x00;
     else
          out=~(lookup[temp]);
  }
}






Tuesday, 12 June 2012

GRADUATE APPRENTICE & TECHNICIAN APPRENTICE @ ISRO LPSC

    Indian space programme was institutionalized in 1969 with the formation of Indian Space Research Organisation [ISRO]. Indian space programme is aimed at promoting the development and application of space science and technology for the socio-economic benefit of the country and also providing valuable service to the Nation in a self reliant manner.

 
Liquid Propulsion Systems Centre (LPSC) is the lead Centre in the area of Liquid    Propulsion for ISRO's Launch Vehicle and Spacecraft programmes. Research and development of Earth Storable, Cryogenic and Semicryogenic propulsion and delivery of Engines, Stages, Associated Control Systems and Components for Launch Vehicle and Spacecraft programmes of ISRO are the main responsibilities of the Centre with its units at Valiamala near Thiruvananthapuram, Bangalore in Karnataka and Mahendragiri in Tamilnadu. The Headquarters located at Valiamala has the responsibilities of R&D.

 
  • Applications are invited for the following training positions under the Apprentices Act 1961 for LPSC units located at VALIAMALA (Near Nedumangadu, Thiruvananthapuram, Kerala) and MAHENDRAGIRI (Near Nagercoil,Tamilnadu):
  • Candidates can register their applications ON-LINE for the training position of GRADUATE APPRENTICE & TECHNICIAN APPRENTICE only from 11-06-2012 14:00 hrs to 20-06-2012 14:00 hrs.
      •  Graduate  Apprentice->BE
      •  Technical Apprentice-> Diploma

Code
Number
Name of the Training Position
Number of Training Positions
Educational Qualification
Stipend
666
VALIAMALA-25, MAHENDRAGIRI-10
FIRST CLASS Bachelor's Degree in Mechanical Engineering from a recognized University.
Rs. 5000/- per month
667
VALIAMALA-03, MAHENDRAGIRI-05
FIRST CLASS Bachelor's Degree in Electrical Engineering from a recognized University.
Rs. 5000/- per month
668
VALIAMALA-05, MAHENDRAGIRI-10
FIRST CLASS Bachelor's Degree in Electronics Engineering from a recognized University.
Rs. 5000/- per month
669
VALIAMALA-02, MAHENDRAGIRI-02
FIRST CLASS Bachelor's Degree in Instrumentation Engineering from a recognized University.
Rs. 5000/- per month
670
VALIAMALA-01, MAHENDRAGIRI-02
FIRST CLASS Bachelor's Degree in Chemical Engineering from a recognized University.
Rs. 5000/- per month
671
VALIAMALA-05, MAHENDRAGIRI-05
FIRST CLASS Bachelor's Degree in Computer Engineering from a recognized University.
Rs. 5000/- per month
672
VALIAMALA-02, MAHENDRAGIRI-04
FIRST CLASS Bachelor's Degree in Civil Engineering from a recognized University.
Rs. 5000/- per month
673
VALIAMALA-06, MAHENDRAGIRI-03
Bachelor's Degree + First Class Degree in Library Science / Library & Information Science
Rs. 5000/- per month
674
VALIAMALA-37, MAHENDRAGIRI-13
FIRST CLASS Diploma in Mechanical Engineering from a recognized Board.
Rs. 3000/- per month
675
VALIAMALA-05, MAHENDRAGIRI-07
FIRST CLASS Diploma in Electrical Engineering from a recognized Board.
Rs. 3000/- per month
676
VALIAMALA-10, MAHENDRAGIRI-12
FIRST CLASS Diploma in Electronics Engineering from a recognized Board.
Rs. 3000/- per month
677
VALIAMALA-01, MAHENDRAGIRI-05
FIRST CLASS Diploma in Chemical Engineering from a recognized Board.
Rs. 3000/- per month
678
VALIAMALA-05
FIRST CLASS Diploma in Computer Engineering from a recognized Board.
Rs. 3000/- per month
679
VALIAMALA-03, MAHENDRAGIRI-07
FIRST CLASS Diploma in Civil Engineering from a recognized Board.
Rs. 3000/- per month
680
MAHENDRAGIRI-15 
First Class Diploma in Commercial Practice/Modern Office Practice.
Rs. 3000/- per month

(Click  on the appropriate name of the post for applying)

  •  Candidates who have acquired qualifying examination in 2010 ,2011 & 2012 (should have acquired the qualification on or before the last date of receipt of application)only are eligible for the above training positions.
  • Age (as on 20-06-2012 ): For Code Nos. 666 to 679 is 35 years and for code No. 680 is 26 years (relaxable by 5 years for SC/ST candidates & 3 years for OBC candidates). Persons with disabilties(PWD) are eligible for upper age relaxation as per Government of India Rules. Click here for General Instructions.
  • Reservations are also applicable. See full details on advt.

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