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Showing posts with label TRAFFIC LIGHT CONTROLLER VLSI CODE. Show all posts
Showing posts with label TRAFFIC LIGHT CONTROLLER VLSI CODE. Show all posts

Friday, 15 June 2012

TRAFFIC LIGHT CONTROLLER VLSI CODE



//TRAFFIC LIGHT CONTROLLER
module tlc(N,E,W,S,clk);

output [2:0] N,E,W,S;
input clk;
parameter s0=3'b000;
parameter s1=3'b001;
parameter s2=3'b010;
parameter s3=3'b011;
parameter s4=3'b100;
parameter s5=3'b101;
parameter s6=3'b110;
parameter s7=3'b111;

parameter R=3'b001;
parameter Y=3'b010;
parameter G=3'b100;

reg [2:0] N,E,W,S;
reg [2:0] state;
integer t=0;

initial    //initialize
 begin
      state <= s0;
      t <= 0;
 end

//--------------TIMING CONTROL-----------
always@(posedge clk)
 begin
//  next_state=state;
  case(state)
   s0:if(t==20) //N=G
         begin
            state=s1;
              t=0;
         end
      else
         t=t+1;
   s1:if(t==5)       //N=Y
         begin
            state=s2;
              t=0;
         end
      else
         t=t+1;
     s2:if(t==20)    //E=G
         begin
            state=s3;
              t=0;
         end
      else
         t=t+1;

   s3:if(t==5)       //E=Y
         begin
            state=s4;
              t=0;
         end
      else
         t=t+1;
               
     s4:if(t==20)    //S=G
         begin
            state=s5;
              t=0;
         end
      else
         t=t+1;

   s5:if(t==5)       //S=Y
         begin
            state=s6;
              t=0;
         end
      else
         t=t+1;
               
     s6:if(t==20)    //W=G
         begin
            state=s7;
              t=0;
         end
      else
         t=t+1;

   s7:if(t==5)       //W=Y
         begin
            state=s0;
              t=0;
         end
      else
         t=t+1;
   default: state=s0;
  endcase
 end  //end of always block

//--------------LIGHT CONTROL-----------
 always @ (state)
  begin
      case (state)
         s0:{N,E,W,S}={G,R,R,R};
            s1:{N,E,W,S}={Y,R,R,R};
            
            s2:{N,E,W,S}={R,G,R,R};
            s3:{N,E,W,S}={R,Y,R,R};
          

            s4:{N,E,W,S}={R,R,G,R};
            s5:{N,E,W,S}={R,R,Y,R};
           
            s6:{N,E,W,S}={R,R,R,G};
            s7:{N,E,W,S}={R,R,R,Y};
            default:{N,E,W,S}={G,R,R,R};
      endcase
  end

endmodule


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