VHDL IEEE PACKAGES - DATA
TYPES – DATA CONVERSIONS
IEEE PACKAGE:
The IEEE library contains several
packages, including the following:
- std_logic_1164: Specifies the STD_LOGIC (8 levels) and STD_ULOGIC (9 levels) multi-valued logic systems.
- std_logic_arith: Specifies the SIGNED and UNSIGNED data types and related arithmetic and comparison operations. It also contains several data conversion functions, which allow one type to be converted into another: conv_integer(p), conv_unsigned(p, b), conv_signed(p, b), conv_std_logic_vector(p, b).
- std_logic_signed: Contains functions that allow operations with STD_LOGIC_VECTOR data to be performed as if the data were of type SIGNED.
- std_logic_unsigned: Contains functions that allow operations with STD_LOGIC_VECTOR data to be performed as if the data were of type UNSIGNED.
- std_logic_textio: Contains functions text i/o, file read & write, etc.
Pre-Defined Data Types
VHDL contains a series of
pre-defined data types, specified through the IEEE 1076 and IEEE 1164
standards. More specifically, such data type definitions can be found
in the following packages / libraries:
- Package standard of library std: Defines BIT, BOOLEAN, INTEGER, and REAL data types.
- Package std_logic_1164 of library ieee: Defines STD_LOGIC and STD_ULOGIC data types.
- Package std_logic_arith of library ieee: Defines SIGNED and UNSIGNED data types, plus several data conversion functions, like conv_integer(p), conv_unsigned(p, b), conv_signed(p, b), and conv_std_logic_vector(p, b).
- Packages std_logic_signed and std_logic_unsigned of library ieee: Contain functions that allow operations with STD_LOGIC_VECTOR data to be performed as if the data were of type SIGNED or UNSIGNED, respectively.
DATA CONVERSIONS:
Several data conversion functions
can be found in the std_logic_arith package of
the ieee library. They are:
- conv_integer(p) : Converts a parameter p of type INTEGER, UNSIGNED, SIGNED, or STD_ULOGIC to an INTEGER value. Notice that STD_LOGIC_VECTOR is not included.
- conv_unsigned(p, b): Converts a parameter p of type INTEGER, UNSIGNED, SIGNED, or STD_ULOGIC to an UNSIGNED value with size b bits.
- conv_signed(p, b): Converts a parameter p of type INTEGER, UNSIGNED, SIGNED, or STD_ULOGIC to a SIGNED value with size b bits.
- conv_std_logic_vector(p, b): Converts a parameter p of type INTEGER, UNSIGNED, SIGNED, or STD_LOGIC to a STD_LOGIC_VECTOR value with size b bits.
The following are the examples for
converting interger to std logic vector, unsigned, singed and std
logic vector to integer, and integer to real & complex, and
integer to string. By converting std logic vector to integer, and
that integer value to string, we can convert std logic vector to
string.
INTEGER TO SLV/UNSIGNED/SIGNED
num is integer
USE
IEEE.NUMERIC_STD.ALL;
dat
<=std_logic_vector(to_unsigned(55,dat'length));
use
ieee.std_logic_arith.all;--NEVER USE STD LOGIC ARITH &
NUMERIC_STD TOGETHER
slv<=
conv_std_logic_vector(num,slv’length);
unsignd :=
conv_unsigned(num,unsignd’length);
signd :=
conv_signed(num,signd’length);
SLV TO INTEGER
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
variable inte:natural;
--dat= std_logic_vector 11 downto 0
inte:=conv_integer(dat); -- to integer
INTEGER TO STRING
report "dat= "
& integer'image(inte); --to string
INTEGER TO REAL/COMPLEX
num is integer
USE
IEEE.MATH_REAL.ALL;
real_num :=
real(inte);
complx :=
complex(inte);
Coming soon: Basic VHDL Syntaxes &
Constructs, Detailed and latest file read write with hexadecimal,
octal, binary data types….. Stay tuned.
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This helps us to do much more better.
Thankyou.
