## Saturday, 24 August 2013

### Verilog Procedural Statement - Blocking And Non-Blocking Statement Synthesis – Reduce Delay - Pipelining

Here we have given an example for the synthesis of procedural statement. The blocking and non-blocking synthesis is different. The delay can also be controlled by grouping the operators. Also the pipelining can be easily added without doing much change.  For easy understanding let us see this for an adder module with 4 inputs of size 8 bit each.

The board chosen in Xilinx ISE is Spartan 3E500 PQ208 package. The code, RTL schematic and timing report is given as follows.

Code 1:

input clk;
input [7:0] a,b,c,d;
output reg [8:0] sum;
reg [8:0] x,y;

always @(posedge clk) begin
sum=a+b+c+d;
end

endmodule

The above is the simple statement for 4 input addition. The synthesis of this code yields 3 adders in series and the delay is “ 3(Td_adder) “, where Td_adder is the delay of an adder block.

Minimum input arrival time before clock: 7.163ns
Maximum output required time after clock: 4.040ns

Code 2:

always @(posedge clk) begin
sum=(a+b)+(c+d);
end

or its equivalent as follows

reg [8:0] x,y;
always @(posedge clk) begin
x=(a+b);
y=(c+d);
sum=x+y;
end

The above is of blocking type & reduces the delay by parallel adding 4 inputs in two adders and their sum is added finally. The synthesis of this code yields 3 adders, with 2 in parallel and the delay is “ 2(Td_adder) “, which is 1/3 times lesser than the Code 1.

Minimum input arrival time before clock: 6.131ns
Maximum output required time after clock: 4.040ns

Code 3:

reg [8:0] x,y;
always @(posedge clk) begin
x<=(a+b);
y<=(c+d);
sum<=x+y;
end

The non-blocking type of Code 2 goes into pipelining concept. Its synthesis of this code simultaneously adds 4 inputs in two adders and their sum is added finally, but as it is non-blocking, the intermediate result is stored in registers. Thus it is pipelined. The delay is “ Td_adder+Td_dff “, where Td_adder is the delay of an adder block and Td_dff is delay of Register/D-flip flop.

Minimum input arrival time before clock: 3.907ns
Maximum output required time after clock: 4.040ns

The comparison table for all the 3 codes is as follows,
 Code Min input arrival time before clock (ns) Max output time after clock  (ns) Resources 1 7.163 4.040 3 adders 2 6.131 4.040 3 adders 3 3.907 4.040 3 adders + 2 DFF + 2 register

Thus proper coding reduces the delay and uses pipelining concept automatically in synthesis. The design optimization can be done manually like these and removing unwanted design units. In the if-else statement, the ELSE part must be used appropriately because it may cause the output or intermediate output to change in unexpected way and can increase area & power.

Goto: Verilog Codes

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