I2C/ TWI Codes - TWI Status Codes - Guide for ATMEL AVR

AVR TWI  STATUS CODES & USAGE

 Features

•      Simple Yet Powerful and Flexible Communication Interface, only two Bus Lines Needed

•      Both Master and Slave Operation Supported

•      Device can Operate as Transmitter or Receiver

•      7-bit Address Space Allows up to 128 Different Slave Addresses

•      Multi-master Arbitration Support

•      Up to 400kHz Data Transfer Speed

•      Slew-rate Limited Output Drivers

•      Noise Suppression Circuitry Rejects Spikes on Bus Lines

•      Fully Programmable Slave Address with General Call Support

•      Address Recognition Causes Wake-up When AVR is in Sleep Mode

Keywords

     MASTER   : Governs the data transmission & slave devices on I²C bus providing clock in SCL

      SLAVE    : That receives or sends data onto bus as per the selection by Master device

            S         : START condition

        Rs/Sr     : REPEATED START condition

R         : Read bit (high level at SDA)

            W        : Write bit (low level at SDA)

A         : Acknowledge bit (low level at SDA)

         NA          : Not acknowledge bit (high level at SDA)

        Data      : 8-bit data byte

P          : STOP condition

         SLA        : Slave Address

MASTER TRANSMIT- SLAVE RECEIVE

Shaded Area describes data transfer from Master controller to slave device, clear block describes data transfer from Slave to master controller.

Following is the sequence we need to follow when writing data:

1.    Send start condition.

2.    Send 7-bit slave address with read/write bit.
If we want to write on to slave device then R/W bit will be 0 and if a read is to be performed then R/W will be set to 1.

Example:   If we want to write on an EEPROM memory with 7bit address as 0x50. we will append write bit to this 7-bit address.

[(MSB) 7-bit address ] [R/W bit (LSB) ] = [ 8-bit address byte with R/W] ie 0b10100000 -> 0xA0

3.    Slave will send Ack bit.

4.    Send data byte to slave and slave will acknowledge every byte, if its last byte to be sent, slave will reply with No-Acknowledge bit (NAK).

5.    In case of EEPROM and certain devices which needs commands to be written into specific register addresses, first data byte is always the subaddress of that I2C device, which denotes the location where the following data is going to be written.

6.    Send stop condition to end data transfer.

NACK:

When SDA remains HIGH during this 9th clock pulse, this is defined as the Not Acknowledge signal. The master can then generate either a STOP condition to abort the transfer, or a repeated START condition to start a new transfer. There are five conditions that lead to the generation of a NACK:

1.    No receiver is present on the bus with the transmitted address so there is no device to respond with an acknowledge.

2.    The receiver is unable to receive or transmit because it’s performing some real-time function and is not ready to start communication with the master.

3.    During the transfer the receiver gets data or commands that it does not understand.

4.    During the transfer, the receiver cannot receive any more data bytes.

5.    A master-receiver needs to signal the end of the transfer to the slave transmitter.

MASTER RECEIVE - SLAVE TRANSMIT (DIRECT READ)

When reading from I2C bus, if you want to read from a specific location or (subaddress) address usually in case of serial EEPROM or RTC etc, we need to send a dummy write byte to put the read pointer to that particular location. this dummy write is demonstrated in figure above. The data flow is explained below:

1.    Send start condition.

2.    Send 7-bit slave address with write bit (R/W = 0).

3.    Send sub address or location on I2C device where u want to read from, after this the internal address pointer of I2C device points to location where u want to read from. This is called dummy write.

4.    Now send a repeated start condition.

5.    Send 7-bit slave address with read bit (R/W = 1).

6.    Now slave will send data to master and master will acknowledge after each byte read. If its the last byte to be read from slave then master will send a not acknowledge.

7.    Master send a stop condition to end the transfer.

FOR SERIAL DEVICES COMBINED FROMAT IS USED.

In case of reading a device with no sub addresses like ADC, DAC or serial devices like RTC, RAM etc then you just need to send slave address with read bit. , the procedure is as in the fig.

C implementation of TWI or I²C

* This is just an example. It is the duty of the programmer to verify correctness of his/her code.

*Note that the code below assumes that several definitions have been made, for example by using include-files.

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