Tuesday, 21 February 2012

ALU VERILOG CODING - TESTBENCH - OUTPUT - GUIDE


VERILOG CODING FOR ALU

Here is a simple verilog code for ALU. It uses case statements to decide the operation to be done on operands.

DESCRIPTION:
     code    -> opcode for alu to do specific operation
     a,b,cin -> input operands
     out,c_out -> output

NOTE: code, a, b, out are 4 bit operands

 
ALU CODE:
     . . . . .

`timescale 1ns / 1ps
module alucode(
    output [3:0] out,
    output c_out,
    input [3:0] code,
    input [3:0] a,b,
    input cin
    );

 parameter andb    =0;
 parameter nandb  =1;
 parameter orb                =2;
 parameter norb     =3;
 parameter xorb=4;
 parameter xnorb=5;
 parameter nota=6;
 parameter lsft=7;
 parameter rsft=8;

 parameter add=9;
 parameter sub=10;
 parameter mul=11;
 parameter div=12;
 parameter mod=13;
 parameter fadd=14;


 reg [3:0] out;
 reg c_out;

 always @ (code,a,b,cin)
          case(code)
                   andb  : out = a & b;
                   nandb : out = ~(a & b);
                   orb   : out = a | b;
                   norb  : out = ~(a | b);
                   xorb  : out = a ^ b;
                   xnorb : out = ~(a ^ b);
                   nota  : out = ~a;
                   lsft  : out = a<<b;
                   rsft  : out = a>>b;
                  
                   add  : out = a + b;
                   sub  : out = a - b;
                   mul  : out = a * b;
                   div  : out = a / b;
                   mod  : out = a % b;
                   fadd : {c_out,out} = a+b+cin;
            default:{c_out,out} = 5'bxxxxx;
   endcase
endmodule

 

OUTPUT WAVEFORM:



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