Friday, 6 March 2015

RTC VERILOG CODE - ELECDUDE

RTC VERILOG CODE - ELECDUDE



            A real-time clock (RTC) is a computer clock (most often in the form of an integrated circuit) that keeps track of the current time. Although the term often refers to the devices in personal computers, servers and embedded systems, RTCs are present in almost any electronic device which needs to keep accurate time. The term is used to avoid confusion with ordinary hardware clocks which are only signals that govern digital electronics, and do not count time in human units.
            Here we've designed an RTC module using Verilog which is very much similar to that of the RTC Chips, but it is a RTL design. This RTL   RTC module can be compiled into a FPGA or PLDs. This module takes up 1Hz clock & starts clocking once enabled. Note that it is a simple design which does not keep the time running when powered off.
            This module is divided into two parts namely, rtc and clock divider. The clock divider module receives the global FPGA clock (say 20MHz) and produces 1Hz clock for the rtc module, which keep track of time.



RTC Module definition:
module rtc(rstn,clk_1hz,enable,second,minute,hour);

 Input & output definition:
input rstn; //active low reset
input enable; //active high enable the clock to work
input clk_1hz; //1Hz clock input
output [5:0] second,minute,hour; //hexadecimal output

 Variable definition:
reg [5:0] s,m,h;
reg s60,m60;

 Output assignment:
assign second=s;
assign minute=m;
assign hour=h;

 Clock counting:
/**************    SECONDS    **************/
always @(negedge rstn or posedge clk_1hz) begin
if (rstn == 0) begin
            s = 0;
            s60=0;
 end
else
if(enable == 1) begin
            if (s == 60-1) begin
                         s = 0;
                         s60= ~s60;
              end
            else
                s = s + 1;
end
end


Clock divider block:
module clock_div(rstn,clkin,enable,clk_1hz);
...
...
parameter FREQ=20e+6; //20MHz input clock
parameter COUNT=FREQ/2;

assign clk_1hz=tc;

always @(negedge rstn or posedge clkin) begin
if (rstn == 0) begin
            i = 0;
            tc=0;  end
else
if(enable == 1) begin
  if (i == COUNT-1) begin
             i = 0;
             tc= ~tc;
  end
  else
             i = i + 1;
end
end
..
...

RTC top module:

module RTC_TOP(rstn,enable,clkin,second,minute,hour);
input rstn; //active low reset
input enable; //active high enable the clock to work
input clkin; //20MHz input clock
wire clk_1hz; //1Hz clock input
output [5:0] second,minute,hour; //hexadecimal output

#module_name    instant_name (ports);
clock_div CLOCK_DIV (rstn,clkin,enable,clk_1hz);
rtc RTC (rstn,clk_1hz,enable,second,minute,hour);

endmodule




The codes are self-explained.  If you've any doubts or need any clarifications, plz don't hesitate to ask us through comments or by mail (admin@elecdude.com).


We welcome your valuable comments and suggestion.
It helps us to do better in future.
Thank you.


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