DATATYPES:
The datatype denotes the type of the data assigned & processed by the variable. But in Verilog it exactly specifies the output type, such as a storage or nonstorage type.
The different datatypes in verilog are as follows
NETS
 
wire

Establishes connectivity, with no logical behavior or functionality implied. (within nonprocedural statements only)

tri

Establishes connectivity, with no logical behavior or functionality implied. This type of net has the same functionality as wire, but is identified distinctively to indicate that it will be threestated in hardware.

wand

A net that is connected to the output of multiple primitives. It models the hardware implementation of a wiredAND, e.g., open collector technology.

wor

A net that is connected to the output of multiple primitives. It models the hardware implementation of a wiredOR, e.g., emitter coupled logic.

supply0

A global net that is connected to the circuit ground.

supply1

A global net that is connected to the power supply.

tri0

A net that is connected to ground by a resistive pulldown connection.

tri1

A net that is connected to the power supply by a resistive pullup connection.

trireg

A net that models the charge stored on a physical net.

REGISTERS
 
reg

Register variables are assigned values by procedural statements within an always or initial block. REG variables can only be output.
Register variables hold their value until an assignment statement changes them. The following are predefined register types: reg, integer (32 bit, 2s complement), real (double precision 64bit), realtime, and time (for time related functions).

MEMORIES
 
Verilog does not have separate datatype for memory array. But can be used from other data type reg
SYNTAX: reg [word_size] <variable>[array_size];
 
STRINGS
 
Verilog does not have a distinct data type for strings. Instead, a string must be stored within a properly sized register by a procedural assignment statement. A properly sized reg (array) has 8 bits of storage for each character of the string that it is to hold.
SYNTAX: reg [8*num_char1: 0] string_holder;
 
CONSTANTS
 
A constant in Verilog is declared with the keyword parameter, which declares and as signs value to the constant. The value of a constant may not be changed during simulation. Constant expressions may be used in the declaration of the value of a constant.
SYNTAX: parameter <variable> = <value>;

EXAMPLES
 
wire out1;

"out1" is a wire that only outputs

reg out2;

"out2" is a register; it stores and outputs a value

reg [7:0] out3;

"out3" is a 8bit register

reg [15:0] out4[7:0];

"out4" is a 8bit register array from 0 to 7

Scope of a variable:
The same net type is not referenced exactly the same within module, task, function. The flow is as given in the figure,
OPERATORS:
Operators in Verilog are the same as they are in other programming languages. They take two values and compare (or otherwise operate on) them to yield a third result. The following table briefs the operator and its examples.
Operator

Argument

Result

Arithmetic

Pair of operands

Binary word

Bitwise

Pair of operands

Binary word

Reduction

Single operand

Bit

Logical

Pair of operands

Boolean value

Relational

Pair of operands

Boolean value

Shift

Single operand

Binary word

Conditional

Three operands

Expression

OPERATOR TYPE

OPERATOR SYMBOL

OPERATION PERFORMED

EXAMPLE
 
Arithmetic

*

Multiply

x= a*b
 
/

Division

x= a/b
 
+

Add

x= a+b
 


Subtract

x= ab
 
%

Modulus

x= a%b
 
+

Unary plus

x= a+b
 


Unary minus

x= ab
 
Logical

!

Logical negation

!a
 
&&

Logical and

a && b
 


Logical or

a  b
 
Relational

>

Greater than

a>b
 
<

Less than

a<b
 
>=

Greater than or equal

a>=b
 
<=

Less than or equal

a<=b
 
Equality

==

Equality

a == b
 
!=

inequality

a != b
 
===

CASE equality

a === b
 
(includes x,z in bitbybit basis)
 
!==

CASE inequality

a !== b
 
(includes x,z in bitbybit basis)
 
Reduction

~

Bitwise negation

x= ~a
 
~&

nand

~&a
 


or

x= a
 
~

nor

x= ~a
 
^

xor

x= ^a
 
^~

xnor

x= ^~a
 
~^

xnor

x= ~^a
 
Shift

>>

Right shift

x= a>> n
 
<<

Left shift

x= a<< n
 
Concatenation

{ }

Concatenation

x= {a,b,n}
 
x={a[3:0],b,a[7:4]}
 
Conditional

?

conditional

x= a<b?1:0

OPERATOR PRECEDENCE
 
Sign complement

HIGHEST

Multiplication Division Modulus







V

Addition Subtraction
 
Shift
 
Relational
 
Reduction
 
Logical
 
Conditional

LOWEST

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