Simple CGPA Calculator for Engg Colleges Anna university, Govt Engg Colleges

              Here is a Simple CGPA/SGPA Calculator for Engineering Colleges under Anna university, Govt Engg Colleges for BE/BTech and ME/MTech cources.

            All you've to do is to edit the subject name, credit points and grade, the SGPA and CGPA are automatically calculated.

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GROUP DISCUSSION - TECHNIQUES & TIPS

GROUP DISCUSSION

                A GD is a methodology used by an organization to guage whether the candidate has certain personality traits and/or skills that it desires in its members. It is used to evaluate the factors such as,

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IMAGE FILE TO TEXT FILE CONVERSION MATLAB – TEXT FILE TO IMAGE FILE CONVERSION MATLAB EXAMPLE

             Here is an example to convert an image into a text file in matlab, for processing in HDL (verilog) or in someother tool. Also the text file is further converted into image file.

           

An image is a 2D matrix. For converting into text file, it needs to be converted into 1D matrix and then to text file using file write in matlab. The image size is also a constraint, so it needs to be fixed for conversion. Then converted to 1D matrix using reshape command. Then write into text file.

A=imread('1.bmp');

B=rgb2gray(A);

disp('Image file read successful');

%figure,imshow(B),title('org');

C=imresize(B,[isize isize]);

figure,imshow(C),title('croped');

d=reshape(C,1,[]);

disp('Reshapping done');

fid = fopen('img.txt', 'wt');

fprintf(fid, '%8d\n', d);

disp('Text file write done');disp(‘ ‘);

fclose(fid);

For converting text file into image, it needs to be converted from 1D matrix and then to image. The image size must same as previous for processing text into image. Then converted to 1D matrix using reshape command. Then write into text file.

·         First, the text file is read using file read  as vector (1D matrix).

·         Then it has to be converted to matrix.

·         Finally transpose to complete it as image.

fidh = fopen('img.txt');

Ah = fscanf(fidh, '%g %g', [1 inf]);

disp('Text file read done');

fclose(fidh);

S1h= vec2mat(Ah,isize,isize);

disp('Vector conversion done');

        %c=imresize(S1,[128 128]);

Sh= transpose(S1h);

Jh=uint8(Sh);

disp('Image is ready');

imwrite(Jh,['newimage','.jpg']);

figure,imshow(Jh),title('IMAGE form TEXT file');

OUTPUT:

Click here to download this Complete tutorial with code

Click here to download matlab code

Goto: MATLAB FILE IO Tutorial

If you have any queries mail us to admin@elecdude.com

Viewers comments are encouraged.

It helps us to do better.

Thank you.

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QUALITIES AND PERSONALITIES FOR GOOD PERSON & SOME EMPLOYEE AND GET HIRED

QUALITIES FOR GOOD PERSON & SOME EMPLOYEE

• LEADERSHIP QUALITIES
• SOCIABLE NATURE
• EASYGOING AND CAREFREE NATURED PERSONALITIES
• BALANCED PSYCHE
• ENTHUSIASTIC PERSONALITIES
• SERIOUS PERSONALITIES

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INTERFACING MULTIPLE TEMPERATURE SENSORS TO AVR – LM35 ATMEGA8

             Here is a simple example to interface multiple temperature sensors to AVR (Atmega8) microcontroller.  Atmega8 is a High-performance, Low-power Atmel®AVR® 8-bit Microcontroller Advanced RISC Architecture with 8KB ISP flash, 1KB RAM, 512B EEPROM, Two 8-bit Timer/Counters with Separate Prescaler, one Compare Mode, One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode, Real Time Counter with Separate Oscillator, Three PWM Channels, 6 multiplexed ADC channels with 10-bit resolution. We have used 2 channels to connect 2 LM35 linear temperature sensors to it.

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MATLAB FILE IO - Syntax - Example Read Write

            This is a simple example for accessing text files in MATLAB. It is always a trouble to process a signal or image in HDL directly. Using this we can convert a signal or an image into a text file and can be used to process in HDL (verilog, VHDL), etc.
             First the required commands for file io are described, followed by the code example for a sine wave write and read.

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APPLICATION ENGINEER -TRAINEE - Corel Technologies

Corel Technologies, Bangaluru

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CGPA CALC Android Apps Developed by Elecdude.com

CGPA CALC

(Simple Andorid apps for CGPA/SGPA for 6 subjects)

   It is Simple Android apps  developed by Elecdude.com,  It performs  six subjects based CGPA/ SGPA calculator
  To calulate CGPA  enter SPGA in "grade point" tab & sum of a sem's credits in "Credit point" tab & click Calculate......

Viewers  comments are encouraged. 

This helps us to much more.

Thank you!!!

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DipTrace - Download - Tutorial - FREE PCB DESIGN SOFTWARE

DipTrace - Download - Tutorial 

FREE PCB DESIGN SOFTWARE 

DipTrace is a complete state-of-the-art PCB Design System. It has auto-routing facility, user friendly library creation, 3D preview of the PCB board. It supports upto 6 layers.

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PTM SPICE MODELS DOWNLOADS - Sub micron nm CMOS Models

          Typical SPICE model files for each future generation are available in ptm.asu.edu/latest.html

          We are providing link to the source site. It is the user's responsibility to read & agree ptm.asu.edu's license agreement before downloading.

PTM releases a new set of models for high-performance applications (PTM HP), incorporating high-k/metal gate and stress effect. 

• 32nm PTM HP model
• 45nm PTM HP model

PTM releases a new version for sub-45nm bulk CMOS, providing new modeling features of metal gate/high-k, gate leakage, temperature effect, and body bias.

• 32nm PTM model for metal gate/high-k CMOS
• 45nm PTM model for metal gate/high-k CMOS

PTM extends the effort to post-Si devices. The first release is for carbon nano-tube FET (CNT-FET). 

• Verilog-A based model card for CNT-FET

PTM for bulk CMOS is released, for 22nm node.  

• 22nm BSIM4 model card for bulk CMOS

A new generation of PTM for bulk CMOS is released, for 130nm to 32nm nodes. It captures the latest technology advances and achieves better scalability and continuity across technology nodes.  

• 32nm BSIM4 model card for bulk CMOS
• 45nm BSIM4 model card for bulk CMOS
• 65nm BSIM4 model card for bulk CMOS
• 90nm BSIM4 model card for bulk CMOS
• 130nm BSIM4 model card for bulk CMOS
• 180nm BSIM3 model card for bulk CMOS

Click here to goto Download page

References

• S. Sinha, G. Yeric, V. Chandra, B. Cline, Y. Cao, "Exploring sub-20nm FinFET design with predictive technology models," to be published at DAC, 2012.
• A. Balijepalli, S. Sinha, Y. Cao, "Compact modeling of carbon nanotube transistor for early stage process-design exploration," ISLPED, pp. 2-7, 2007.
• W. Zhao, Y. Cao, "New generation of Predictive Technology Model for sub-45nm early design exploration," IEEE Transactions on Electron Devices, vol. 53, no. 11, pp. 2816-2823, November 2006.
• Y. Cao, T. Sato, D. Sylvester, M. Orshansky, C. Hu, "New paradigm of predictive MOSFET and interconnect modeling for early circuit design," pp. 201-204, CICC, 2000.

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BACK END TOOL PROGRAMMING TUTORIAL – TANNER TUTORIAL –INVERTER EXAMPLE 180nm CMOS TECH – POWER ANALYSIS USING TANNER

This tutorial gives general procedure for working with Tanner EDA design suite- Sedit & Tspice. Power analysis steps are also added in this using 180nm TSMC CMOS technology.

1.  Open SEDIT, then select FILE à New Design

2.  Give a name for the design & select the required folder for the design.

3.  Then select  CELL à NEW VIEW  for drawing the schematic.

4.  Then give a name for the schematic & clik OK.

5.  Then click on add in the libraries window for adding the Tanner library file.

6.  The browse for the library file in MY DOCUMENTS/TANNER TOOLS V 13.0/LIBRARIES/ALL/ALL.TANNER

7.   Place the NMOS of inverter as shown in the figure, from DEVICES library.

8.  Similarly place the PMOS, place supply (VDD) & ground (GND) from MISC library.

9.  To edit the parameters of the device, select the device & press CTRL+E, and can be edited in the PROPERTIES window in the right.

10.             Then place the INPUT & OUTPUT port. You can give any name for ports before placing.

11.              Now using the wire tool, make the circuit connections of the inverter.

12.              The BULK pin of PMOS should be connected to VDD. Similarly for NMOS connect to GND.

13.             Then specify a symbol for the inverter by selecting, CELL àUPDATE SYMBOL.

14.             Default symbol will be a square. You can modify the symbol by using drawing tools in the toolbar.

15.             After drawing the symbol, save the design & close it.

NEXT STEP IS TO CREATE THE TESTING CIRCUIT

 1.  Create a new design.

 2.  Then add the previous design

3.  All the default libraries will be included along with it. 

4.  Now drag & drop the INVERTER cell symbol into the design. 

5.  Place the DC voltage source for VDD from SPICE ELEMENTS library. 

6.  Before placing it, change the voltage as required. (for 180nm technology, VDD is about 2.5V) 

7.  Now for the input to inverter, choose the INTERFACE as BIT. Change the properties as needed 

8.  After placin, right click on empty region. 

9.  Then place a load capacitor 

10.             Wire the devices. 

11.         Save design 

12.             Browse for the required model file & select OK. 

13.             Select TRANSICENT /FOURIER ANALYSIS. Set the maximum step time as 2n & Stop time as req. (here 200n) 

14.              To print the voltages select PRINT VOLTAGE from SPICE_COMMANDS library, place on the required node (here on input & output nodes)

15.             Save design and clik on START SIMULATION ICON. The simulated output waveform will be opened if simulated correctly without any errors.

16.             Alternatively, click on  OPEN IN T-SPICE to view the netlist & to simulate directly in T-Spice. Save the netlist in req. location before simulating in t-spice.

       SPICE NETLIST EXTENSION : .SP

This is the netlist of our inverter test circuit. The inverter is instantiated by using sub-circuit definition.

 17. To see the power analysis output, open the *.out file of the corresponding netlist.

 18. Goto the end of the out file to see the power analysis result.

For simplicity, the test circuit description is given in PDF. 

CLICK HERE TO DOWNLOAD THE COMPLETE TUTORIAL IN PDF

 Please feel free to get your doubts cleared. Also you can suggest if you've any different ideas.

Stay tuned for BASIC GATES & much more in upcoming posts.......

Viewers  comments are encouraged. 

This helps us to much more.

Thank you!!!

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POWERGRID - FIELD ENGINEER VACANCY 2013 - BE ECE

POWERGRID, A leading Navratna PSU under the Ministry of Power, Govt. of India and one of the largest Transmission Utilities in the world has been entrusted with establishing and strengthening Optical fibre connectivity to the Gram Panchayats under National Optical Fibre Network Project  (NOFN).

POWERGRID is on look out of young and bright experienced professionals for engagement purely on temporary (Contractual) basis  with consolidated remuneration  for a period of  24 months or till  completion of project whichever is earlier for execution of NOFN  consultancy Project in the state of Andhra Pradesh.

Sl.No	Name of the Post	Post Code	Vacancies	Vacancies breakup	Essential Qualification
1	Field Engineer (on Temporary Contract Basis)	CFE	52	SC-8 ST-3 OBC(NCL)-13 UR-28 Total = 52 PwD* - 02 (OH- OA, OL)	B.E/ B.Tech/ B.SC(Engg)/ AMIE in Electronics & Communication Engineering discipline from recognized University/ Institute with minimum 55% marks.

AGE LIMIT: 29 years as on 28.02.2013

APPLICATION FEE:  Rs 200/-

LAST DATE TO APPLY: 28th February 2013.

EXPERIENCE:

Should have one year Post qualification experience in design/ engineering of Optical Fibre Network,  adequate experience of Construction, Testing & Commissioning, Operation & Maintenance, activities of Optical Fibre Network System (SDH/  DWDM/ G-PON/MPLS etc.). Experience in  PSU/Listed company particularly in Telecom sector shall be preferred.

SELECTION PROCESS:

The selection will be on the basis of Personal Interview.      

However, the Management reserves the right to raise the minimum eligibility standards/criteria and / or to conduct a screening test, to restrict the number of candidates to be called for Personal Interview, if so required.

Screening test, if conducted, shall be an objective type test of one hour duration for elimination purpose only and shall not carry any weightage in final merit.

Offer of engagement shall be sent to the candidates found suitable in interview in the order of merit and depending upon the number of vacancies.  The final engagement of selected  candidates  is subject to  their medical fitness as per company’s standards and other joining formalities. No relaxation in health standards is allowed.

The engagement is purely temporary in nature and on contract basis for a period of two years or completion of project whichever is earlier. Contractual engagement will automatically come to an end on the expiry of aforesaid period of two years or completion of project whichever is earlier and persons will have no right or claim to continue with POWERGRID beyond the specified terms or seek regular employment.

Contract personnel will be paid consolidated  monthly remuneration as under:
Name of the Post	1st year	2nd Year
Field Engineer	Rs.30,000/-	Rs.33,000/-

HOW TO APPLY

Interested eligible candidates should send their applications completed in all respects in the prescribed proforma alongwith non-refundable application fees as mentioned above in form of A/c Payee Demand Draft and/or attested copy of Caste (SC/ST/OBC-NCL)/ Disability (PwD)/Discharge (Ex-SM) certificate, as applicable, Qualification certificate, Date of birth certificate and experience certificate to the following address super scribing the envelop with “ Application for the Post of FIELD ENGINEER ”Post cod CFE” In POWERGRID, SRTS-I by ORDINARY POST only. Candidates should write their name and address at the reverse side of Bank draft.

THE CHIEF MANAGER(HR) / HOP

POWER GRID CORPORATION OF INDIA LTD.

SRTS-I, REGIONAL HEADQUARTERS

# 6-6-8/32 & 395E, KAVADIGUDA MAIN ROAD,

SECUNDERABAD – 500080 (ANDHRA PRADESH)

 CLICK HERE TO VIEW APPLICATION IN PDF

READERS COMMENTS ARE ENCOURAGED.

IT HELPS US TO DO MUCH MORE BETTER.

THANK YOU!!!

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GUIDE LINE FOR FRESH ENGINEERING STUDENTS

GUIDE LINE FOR FRESH ENGINEERING STUDENTS FROM RURAL

Attention Engineering Students!!!! Get prepared yourself to face Campus interview & be placed…..

  Here we give some general tips for preparing yourself to face an interview at an early stage.

 

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GATE 2013 - CSIT - ECE - EEE - MECH - INSTRUMENTAL - PRODUCTION - QUESTION PAPER & ANSWER KEY DOWNLOAD

GATE 2013 - CSIT - ECE - EEE - MECH - INSTRUMENTAL - PRODUCTION - QUESTION PAPER & ANSWER KEY DOWNLOAD

ELECTRONICS & COMMUNICATION

• Q&A with Key

ELECTRICAL & ELECTRONICS

• Q&A with Key

COMPUTER SCIENCE & IT

• Q&A with Key

MECHANICAL

• Q&A with Key

INSTRUMENTAL

• Q&A with Key

PRODUCTION

• Q&A with Key

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