Wednesday, 3 April 2013


This tutorial gives general procedure for working with Tanner EDA design suite- Sedit & Tspice. Power analysis steps are also added in this using 180nm TSMC CMOS technology.

1.  Open SEDIT, then select FILE à New Design

2.  Give a name for the design & select the required folder for the design.

3.  Then select  CELL à NEW VIEW  for drawing the schematic.

4.  Then give a name for the schematic & clik OK.

5.  Then click on add in the libraries window for adding the Tanner library file.

6.  The browse for the library file in MY DOCUMENTS/TANNER TOOLS V 13.0/LIBRARIES/ALL/ALL.TANNER

7.   Place the NMOS of inverter as shown in the figure, from DEVICES library.

8.  Similarly place the PMOS, place supply (VDD) & ground (GND) from MISC library.

9.  To edit the parameters of the device, select the device & press CTRL+E, and can be edited in the PROPERTIES window in the right.

10.             Then place the INPUT & OUTPUT port. You can give any name for ports before placing.

11.              Now using the wire tool, make the circuit connections of the inverter.

12.              The BULK pin of PMOS should be connected to VDD. Similarly for NMOS connect to GND.

13.             Then specify a symbol for the inverter by selecting, CELL àUPDATE SYMBOL.

14.             Default symbol will be a square. You can modify the symbol by using drawing tools in the toolbar.

15.             After drawing the symbol, save the design & close it.

 1.  Create a new design.
 2.  Then add the previous design
3.  All the default libraries will be included along with it. 
4.  Now drag & drop the INVERTER cell symbol into the design. 
5.  Place the DC voltage source for VDD from SPICE ELEMENTS library. 
6.  Before placing it, change the voltage as required. (for 180nm technology, VDD is about 2.5V) 
7.  Now for the input to inverter, choose the INTERFACE as BIT. Change the properties as needed 
8.  After placin, right click on empty region. 
9.  Then place a load capacitor 
10.             Wire the devices. 
11.         Save design 
12.             Browse for the required model file & select OK. 
13.             Select TRANSICENT /FOURIER ANALYSIS. Set the maximum step time as 2n & Stop time as req. (here 200n
14.              To print the voltages select PRINT VOLTAGE from SPICE_COMMANDS library, place on the required node (here on input & output nodes)
15.             Save design and clik on START SIMULATION ICON. The simulated output waveform will be opened if simulated correctly without any errors.

16.             Alternatively, click on  OPEN IN T-SPICE to view the netlist & to simulate directly in T-Spice. Save the netlist in req. location before simulating in t-spice.
This is the netlist of our inverter test circuit. The inverter is instantiated by using sub-circuit definition.

 17. To see the power analysis output, open the *.out file of the corresponding netlist.
 18. Goto the end of the out file to see the power analysis result.

For simplicity, the test circuit description is given in PDF. 

 Please feel free to get your doubts cleared. Also you can suggest if you've any different ideas.

Stay tuned for BASIC GATES & much more in upcoming posts.......

Viewers  comments are encouraged. 
This helps us to much more.
Thank you!!!



  1. i am getting the following warnings and error ....what do i do??

    Warning : "Cell0.sp" line 25 Invalid binned model NMOS
    : "Cell0.sp" line 25 Binned models must define LMIN, LMAX, WMIN, and WMAX, and have a name suffix of .# (e.g. nch.1)
    Warning : "Cell0.sp" line 88 Invalid binned model PMOS
    : "Cell0.sp" line 88 Binned models must define LMIN, LMAX, WMIN, and WMAX, and have a name suffix of .# (e.g. nch.1)

    model NMOS, 1e-007 <= width < 0.0001, 1e-007 <= length < 1e-007

    Unmatched usages of model NMOS:
    device MNMOS_1, width= 3e-006, length= 1e-006

    Fatal Error : Size match failed for model "NMOS"


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