Thursday, 29 January 2015

COMMONLY USED VHDL CONSTURCTS

COMMONLY USED VHDL CONSTURCTS

-- ********************** VHDL EXAMPLE CONTRUCTS

******************************************

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.NUMERIC_STD.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

USE IEEE.STD_LOGIC_SIGNED.ALL;

USE IEEE.STD_LOGIC_TEXTIO.ALL;

USE STD.TEXTIO.ALL;

NUMERIC_STD TOGETHER

use work.my_pckg.all;

-- USE IEEE.STD_LOGIC_ARITH.ALL; --NEVER USE STD LOGIC ARITH &

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-- To print current simulation time

report "Current Simulation time @ " & time'image(now);

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-- GENERIC EXAMPLE

ENTITY parity_det IS

    GENERIC (n : INTEGER := 7);

    PORT ( input: IN BIT_VECTOR (n DOWNTO 0);

               output: OUT BIT);

END parity_det;

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-- CLOCK signal generation

signal sys_clk : bit := '0';

constant sys_clk_period : time := 100 ns; -- Clock period definitions

-- Clock process definitions

sys_clk_process :process

 begin

sys_clk <= '0';

wait for sys_clk_period/2;

sys_clk <= '1';

wait for sys_clk_period/2;

 end process;

 -- Clock process definition - Method 2

sys_clk_process :process

 begin

 end process;

sys_clk <= not sys_clk after sys_clk_period/2;

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--Clock Generator Procedure - Period & Offset defined

procedure clk_gen(signal clk: out std_logic; constant OFS: time; constant PERIOD:

time) is

begin

-- Check the arguments

assert ((PERIOD/2) /= 0 fs) report "clk_plain: High time is zero; time resolution to

large for frequency" severity FAILURE;

-- Generate a clock cycle

 clk <= '0';

 wait for OFS;

 loop

  clk <= '1';

  wait for PERIOD/2;

  clk <= '0';

  wait for PERIOD/2;

 end loop;

end procedure;

clk_gen(clk,12 ns,20 ns); --PERIOD= 20ns

clk_gen(clk,12 ns,(1 sec/100.0E+6)); --Freq= 100MHz

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-- FUNCTION EXAMPLE

FUNCTION conv_integer (SIGNAL vector: STD_LOGIC_VECTOR)

RETURN INTEGER IS

VARIABLE result: INTEGER RANGE 0 TO 2**vector'LENGTH-1;

BEGIN

IF (vector(vector'HIGH)='1') THEN

result:=1;

ELSE

result:=0;

END IF;

FOR i IN (vector'HIGH-1) DOWNTO (vector'LOW) LOOP

result:=result*2;

IF(vector(i)='1') THEN

END IF;

END LOOP;

RETURN result;

result:=result+1;

END conv_integer;

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-- Stimulus process example

stim_proc: process

begin

 -- hold reset state for 100ms.

 wait for 100 ns;

 --Sample way of setting inputs - reset used as a redundant example.

reset <= '1';

wait for 10 ns;

reset <= '0';

wait for 10 ns;

wait;

end process;

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-- SOME COMMONLY USED CONTROL STRUCTURE SYNTAXES

------ With WHEN/ELSE -------------------------

outp <= "000" WHEN (inp='0' OR reset='1') ELSE

"001" WHEN ctl='1' ELSE

"010";

---- With WITH/SELECT/WHEN --------------------

WITH control SELECT

output <= "000" WHEN reset,

"111" WHEN set,

UNAFFECTED WHEN OTHERS;

---- with WITH/SELECT/WHEN -----

WITH sel SELECT

   y <= a WHEN "00", -- notice "," instead of ";"

b WHEN "01",

c WHEN "10",

d WHEN OTHERS; -- cannot be "d WHEN "11" "

---- CASE ------------------------

case sel is

when "00"=> y <= a;

when "01"=> y <= b;

when "10"=> y <= c; --when "00"=> y <= a;

when others=> y<=d;

end case;

---- tristate buffer WHEN/ELSE

output <= input WHEN (ena='0') ELSE

  (OTHERS => 'Z');

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-- Detect Rising edge

IF RISING_EDGE(clk)

-- Detect falling edge

if falling_edge (clk)

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--State Machine Declaration

type STATES is (s0,s1,s2);

signal cur,nxt: STATES;

 StateTrans:process (clk, rstb)

 begin

if (rstb = '0') then

cur <= s0;

elsif (RISING_EDGE(clk)) then

cur <= nxt;

end if;

 end process StateTrans;

 FSM_combi:process(cur,<inputs>) begin

case cur is

 when s0=> nxt<=s1;

 when s1=> nxt<=s2;

 when s2=> nxt<=s0;

 when OTHERS=> nxt<=s0;

end case;

 end process FSM_combi;

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--MEMORY ARRAY - RAM ROM

type mem_array is array (0 to 15) of std_logic_vector (7 downto 0);

constant rom: mem_array := ( “11111011”, “00010010”, “10011011”, “10010011”,

“01011011”, “00111010”,

“00010010”, “10101001”, “00110110”, “11011011”, “01010010”);

data <= rom(address); -- data = STD vector & address= integer

“11111011”, “00010010”, “10100011”, “10011010”, “01111011”,

signal RAM: mem_array := ( “11111011”, “00010010”, “10011011”, “10010011”,

“01011011”, “00111010”,

“00010010”, “10101001”, “00110110”, “11011011”, “01010010”);

“11111011”, “00010010”, “10100011”, “10011010”, “01111011”,

data <= RAM(conv_integer(addrs)); -- data & addrs = STD vector



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