To enter any of the six sleep modes, set the SE bit in MCUCR and set the required sleep mode, then a SLEEP instruction must be executed.
The SM2, SM1 and SM0 bits in the MCUCR Register select which sleep mode (Idle, ADC Noise Reduction, Power-down, Power-save, Standby, or Extended Standby) will be activated by the SLEEP instruction.
MCU Control Register – MCUCR
| Bit MCUCR | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| SM2 | SE | SM1 | SM0 | ISC11 | ISC10 | ISC01 | ISC00 |
Bit 7 – SE: Sleep Enable
Bits 6:4 – SM2..0: Sleep Mode Select Bits 2, 1, and 0
| SM2 | SM1 | SM0 | Sleep Mode | STOPED | Wake-Up INTERRUPT Source |
| 0 | 0 | 0 | Idle | CPU only | External & all internal interrupts (halts clkCPU and clkFLASH) |
| 0 | 0 | 1 | ADC Noise Reduction | CPU & Timers 0,1 (halts clkI/O, clkCPU, and clkFLASH) | ADC Conversion Complete interrupt, only an External Reset, a Watchdog Reset, a Brown-out Reset, a Two-wire Serial Interface address match interrupt, a Timer/Counter2 interrupt, an SPM/EEPROM ready interrupt, or an external level interrupt on INT0 or INT1 |
| 0 | 1 | 0 | Power-down# | External Oscillator Fclk & its functions | External Reset, a Watchdog Reset, a Brown-out Reset, a Two-wire Serial Interface address match interrupt, or an external level interrupt on INT0 or INT1 |
| 0 | 1 | 1 | Power-save# | same as Power down except T2_Async | T2 Async INT, External Reset, a Watchdog Reset, a Brown-out Reset, a Two-wire Serial Interface address match interrupt, or an external level interrupt on INT0 or INT1 |
| 1 | 0 | 0 | Reserved | ||
| 1 | 0 | 1 | |||
| 1 | 1 | 0 | Standby* | · This mode is identical to Power-down, only if an* external crystal/resonator clock option is selected, with the exception that the Oscillator is kept running. · From Standby/Extended standby mode, the device wakes up in 6 clock cycles. | |
| 1 | 1 | 1 | Extended Standby | ||
#- the wake up delay is according to start-up delay set by CKSEL fuses
Bit 3, 2 – ISC11, ISC10: Interrupt Sense Control 1 Bit 1 and Bit 0 Bit 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0 Interrupt x (x=0 or 1) Sense Control ISCx1 ISCx0 Description 0 0 The low level of INTx generates an interrupt request 0 1 Any logical change on INTx generates an interrupt request 1 0 The falling edge of INTx generates an interrupt request 1 1 The rising edge of INTx generates an interrupt request General Interrupt Control Register – GICR Bit 7 6 5 4 3 2 1 0 INT1 INT0 INT2 – – – IVSEL IVCE Bit 6 – INT0: External Interrupt Request 0 Enable {0=disable, 1=ENABLED}
Here we present a simple GCC code done using AVR Studio4 in Atmega 16 MCU. The header file which is used for governing the sleep process is <avr/sleep.h>. Different Sleep modes are described in the previous table. External Interrupt0 is used as wake-up source.
Setting Sleep Mode: set_sleep_mode(SLEEP_MODE_IDLE);
set_sleep_mode(MODE)
Arg: MODE= SLEEP_MODE_IDLE
SLEEP_MODE_ADC
SLEEP_MODE_PWR_DOWN
SLEEP_MODE_PWR_SAVE
SLEEP_MODE_STANDBY
SLEEP_MODE_EXT_STANDBY
Entering Sleep Mode: sleep_mode();
Setting INT0 interrupt:
//ext int0 @falling edge
CLEARBIT(DDRD,2)
SETBIT(PORTD,2)
SETBIT(GICR,INT0)
MCUCR|= ( (1<<ISC01)|(0<<ISC00) );
Enabling Global Interrupt: sei();
The code initializes the LCD display and sets INT0 in falling edge interrupt, IDLE sleep mode and enters sleep mode.
When a falling edge on INT0 is detected INT0_ISR is executed which increments count variable & displays it on LCD. Then it returns to main function, which again enters into sleep mode. PB0 is set in ISR & cleared in main loop just for visual experience of ISR execution time.
Click here to download the code.
The circuit for this demo is
The Proteus Simulation output is...
This is an example implementation of Sleep mode. This sleep functions are common for most of the AVR MCU family, which will be taken care of <avr/sleep.h> header file.
