Verilog Procedural Statement - Blocking And Non-Blocking Statement Synthesis – Reduce Delay - Pipelining

         Here we have given an example for the synthesis of procedural statement. The blocking and non-blocking synthesis is different. The delay can also be controlled by grouping the operators. Also the pipelining can be easily added without doing much change.  For easy understanding let us see this for an adder module with 4 inputs of size 8 bit each. 

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ISRO LPSC Graduate Apprentice & Technician Apprentice 2013 - Tamil Nadu Kerala

ISRO LPSC invites applications for the following training positions under the Apprentices Act 1961 for LPSC units located at

•      VALIAMALA (Near Nedumangadu,Thiruvananthapuram,Kerala)
  
•     MAHENDRAGIRI (Near Nagercoil,Tamilnadu)

form candidates who have passed Degree/Diploma from a recognized University/Board coming under Southern Region of Board of Apprenticeship Training (ie Kerala, Karnataka, Tamil Nadu and Andhra Pradesh.

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INTERRUPTS IN AVR MICROCONTROLLER - ATMEGA 8/16/32

 An interrupt is an external or internal event that interrupts the microcontroller to inform it that a device needs its service.

 A single microcontroller can serve several devices by two ways a) interrupt and b) polling

 ·        Interrupts

o   Whenever any device needs its service, the device notifies the microcontroller by sending it an interrupt signal

o   Upon receiving an interrupt signal, the microcontroller interrupts whatever it is doing and serves the device

o   The program which is associated with the interrupt is called the interrupt service routine (ISR) or interrupt handler

o   For every interrupt, there must be an interrupt service routine (ISR), or interrupt handler

·        Polling

o   The polling method is not efficient, since it wastes much of the microcontroller’s time by polling devices that do not need  service

 

ISR or Interrupt Service Routine or Interrupt Handler defines the task that is needed to be performed when the interrupt occurs. It is the set of codes for the controller to execute on the occurrence of the interrupt.  The following table gives the interrupt sources in AVR Atmega 8 microcontroller, but most of this is common for the Atmega series controllers such as Atmega 16, Atmega 168, Atmega 32, etc

     AVR microcontroller has many interrupt sources but each has a different vector name which is used by the AVR studio compiler. But the vector name is specific to a interrupt source, which has a different name from the interrupt source name. The following table shows the vector name used by the compiler. The ISR is function whose input is the "INTERRUPT VECTOR NAME". These Vector Name is mapped into vector addresses.

VECTOR NAME	INTERRUPT SOURCE
INT0_vect	External INT0
INT1_vect	External INT1
TIMER2_COMP_vect	Timer 2 Compare match
TIMER2_OVF_vect	Timer 2 overflow
TIMER1_CAPT_vect	Timer1 Input Capture
TIMER1_COMPA_vect	Timer1 Compare A match
TIMER1_COMPB_vect	Timer1 Compare B match
TIMER1_OVF_vect	Timer1 Overflow
TIMER0_OVF_vect	Timer0 Overflow
SPI_STC_vect	SPI complete
USART_RXC_vect	USART RX Complete
USART_UDRE_vect	USART UDR EMPTY
USART_TXC_vect	USART TX Complete
ADC_vect	ADC Conv Complete
EE_RDY_vect	EEPROM Ready/Complete
ANA_COMP_vect	Analog Comparator i/p change
TWI_vect	TWI or I2C done/complete/receive

        To add the ISR for an interrupt source, just type the vector name in the function ISR(<vect_name>).  All other interrupts are disabled when controller is servicing (executing) an ISR and automatically enabled when the execution is completed. The AVR accomplishes this by disabling the global interrupt enable {sei();} and disable {cli();} function. Don’t forget to enable global interrupt enable flag before going into the infinite program loop, else the interrupt will not be served.

Syntax:
    ISR(<vector_name>)
      {   
          //code for the ISR
      }

 Example:

ISR(INT0_vect)

{//1 int0

}

ISR(TIMER1_COMPA_vect)

{//1 int0

}

 In order to have smooth interrupt functions follow the procedure,

1.    Choose the required interrupt source and its int type & trigger, read its registers description.

2.    Set the interrupt type & trigger method of the corresponding interrupt in its control registers and status register.

3.    Set the interrupt enable bit in control register.

4.    Set the global interrupt enable bit using “ sei(); ” command.

NOTE: If two or more interrupt sources are used in the program, then the global interrupt enable bit must be set after initializing all the interrupt sources.

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TRANSISTOR CODES AND CHOOSING by WWW.ELECDUDE.COM

TRANSISTOR CODES
There are three main series of transistor codes used in the UK:

* Codes beginning with B (or A), for example BC108, BC478
   
    The first letter denotes the material
                                   B - SILICON
                                   A - GERMANIUM

   The second letter denotes the type of the transistor
                                   C-LOW PWER AUDIO FREQUENCY
                                   D-HIGH POWER AUDIO GREQUENCY
                                   F-LOW POWER HIGH FREQUENCY
                                   The rest of the code identifies the particular transistor

         There is no obvious logic to the numbering system. Sometimes a letter is added to the end (eg BC108C) to identify a special version of the main type, for example a higher current gain or a different case style. If a project specifies a higher gain version (BC108C) it must be used, but if the general code is given (BC108) any transistor with that code is suitable.

*Codes beginning with TIP, for example TIP31A

           TIP refers to the manufacturer: Texas Instruments Power transistor. The letter at the end identifies versions with different voltage ratings.

* Codes beginning with 2N, for example 2N3053
    
           The initial '2N' identifies the part as a transistor and the rest of the code identifies the particular transistor. There is no obvious logic to the numbering system.


Choosing a transistor

         Most projects will specify a particular transistor, but if necessary you can usually substitute an
equivalent transistor from the wide range available. The most important properties to look for
are the maximum collector current IC and the current gain hFE. To make selection easier most
suppliers group their transistors in categories determined either by their typical use or
maximum power rating.
         To make a final choice you will need to consult the tables of technical data which are normally
provided in catalogues. They contain a great deal of useful information but they can be difficult
to understand if you are not familiar with the abbreviations used. The table below shows the
most important technical data for some popular transistors, tables in catalogues and reference
books will usually show additional information but this is unlikely to be useful unless you are
experienced. The quantities shown in the table are explained below.

NPN transistors
Code Structure Case style IC max. VCE max. hFE min. Ptot max. Category (typical use) Possible substitutesBC107 NPN TO18 100mA 45V 110 300mW Audio, low
power BC182 BC547
BC108 NPN TO18 100mA 20V 110 300mW
General
purpose, low
power
BC108C BC183
BC548
BC108C NPN TO18 100mA 20V 420 600mW
General
purpose, low
power
BC109 NPN TO18 200mA 20V 200 300mW
Audio (low
noise),low
power
BC184 BC549
BC182 NPN TO92C 100mA 50V 100 350mW
General
purpose, low
power
BC107 BC182L
BC182L NPN TO92A 100mA 50V 100 350mW
General
purpose, low
power
BC107 BC182
BC547B NPN TO92C 100mA 45V 200 500mW Audio, low
power BC107B
BC548B NPN TO92C 100mA 30V 220 500mW

General
purpose, low
power
BC108B
BC549B NPN TO92C 100mA 30V 240 625mW
Audio (low
noise), low
power
BC109
2N3053 NPN TO39 700mA 40V 50 500mW
General
purpose, low
power
BFY51
BFY51 NPN TO39 1A 30V 40 800mW
General
purpose,
medium power
BC639
BC639 NPN TO92A 1A 80V 40 800mW
General
purpose,
medium power
BFY51
TIP29A NPN TO220 1A 60V 40 30W
General
purpose, high
power
TIP31A NPN TO220 3A 60V 10 40W
General
purpose, high
power
TIP31C TIP41A
TIP31C NPN TO220 3A 100V 10 40W
General
purpose, high
power
TIP31A TIP41A
TIP41A NPN TO220 6A 60V 15 65W
General
purpose, high
power
2N3055 NPN TO3 15A 60V 20 117W
General
purpose, high
power
Please note: the data in this table was compiled from several sources which are not entirely consistent!
Most of the discrepancies are minor, but please consult information from your supplier if you require precise
data.
PNP transistors
Code Structure Case
style
IC
max.
VCE
max.
hFE
min.
Ptot
max.
Category
(typical
use)
Possible
substitutes

BC177 PNP TO18 100mA 45V 125 300mW Audio, low
power BC477
BC178 PNP TO18 200mA 25V 120 600mW
General
purpose, low
power
BC478
BC179 PNP TO18 200mA 20V 180 600mW
Audio (low
noise), low
power
BC477 PNP TO18 150mA 80V 125 360mW Audio, low
power BC177
BC478 PNP TO18 150mA 40V 125 360mW
General
purpose, low
power
BC178
TIP32A PNP TO220 3A 60V 25 40W
General
purpose, high
power
TIP32C
TIP32C PNP TO220 3A 100V 10 40W
General
purpose, high
power
TIP32A
Please note: the data in this table was compiled from several sources which are not entirely consistent!
Most of the discrepancies are minor, but please consult information from your supplier if you require precise
data.
Structure This shows the type of transistor, NPN or PNP. The polarities of
the two types are different, so if you are looking for a substitute it
must be the same type.
Case style There is a diagram showing the leads for some of the most
common case styles in the Connecting section above. This
information is also available in suppliers' catalogues.
IC max. Maximum collector current.

VCE max. Maximum voltage across the collector-emitter junction.
You can ignore this rating in low voltage circuits.
http://www.kpsec.freeuk.com/components/tran.htm (7 of 9)11/25/2008 8:03:29 PM
Transistors
hFE This is the current gain (strictly the DC current gain). The
guaranteed minimum value is given because the actual value
varies from transistor to transistor - even for those of the same
type! Note that current gain is just a number so it has no units.
The gain is often quoted at a particular collector current IC which is usually in
the middle of the transistor's range, for example '100@20mA' means the
gain is at least 100 at 20mA. Sometimes minimum and maximum values are
given. Since the gain is roughly constant for various currents but it varies
from transistor to transistor this detail is only really of interest to experts.
Why hFE? It is one of a whole series of parameters for transistors, each
with their own symbol. There are too many to explain here.
Ptot max. Maximum total power which can be developed in the transistor,
note that a heat sink will be required to achieve the maximum
rating. This rating is important for transistors operating as
amplifiers, the power is roughly IC × VCE. For transistors
operating as switches the maximum collector current (IC max.) is
more important.
Category This shows the typical use for the transistor, it is a good starting
point when looking for a substitute. Catalogues may have
separate tables for different categories.
Possible substitutes These are transistors with similar electrical properties which will
be suitable substitutes in most circuits. However, they may have
a different case style so you will need to take care when placing
them on the circuit board.

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MODELSIM TUTORIAL – WORKING WITH TESTBENCH – GETTING STARTED

GETTING STARTED WITH MENTOR GRAPH MODELSIM SE 6

              Mentorgraph Modelsim is an simulation tool and is being used in many industries for simulation and code verification. This tool can be used for simulation along with Xilinx (upto ISE 9.x). But recent Xilinx edition have withdrawn other third-party simulation & addon support.

              But this is an easy tool when you need to just simulate and verify the code & its correctness. But the steps are likely to be confusing. Here we present an example for creating a new design file and simulating it in Modelsim version SE6.

1.      Open ModelSim SE6.

2.      Then, goto FILE->CHANGE DIRECTORY  to change the current working directory.

3.      Choose your required folder. Here I choose "C:\My Projects".

4.      Now create a new work library by, FILE-> NEW-> LIBRARY.

5.      In create, select 'a new lib & logical map to it' and give Library Name and Library Physical Name as "work".

6.      To create a new verilog file, choose FILE->NEW-> SOURCE-> VERILOG

7.      Type the verilog code and save it. Here a positive edge triggered D flip flop synchronous reset and preset is used.

module dffr_pr (d,clk,preb,rstb, q,qb);
  input d,clk,preb,rstb;
  output reg q;
  output qb;
    assign qb=~q;
    always @ (posedge clk) begin
    if(rstb==0)
      q=0;
    else if(preb==0)
            q=1;
         else
            q=d;
  end
  endmodule

8.      Now compile the code by, COMPILE->COMPILE. In the pop-up window select your code file and compile it. If done successfully, we can see the report in transcript window. And the module will be added under the work directory.

9.      To simulate the module double click the module name under the Library window. This will start simulating with full optimization. Check the report in transcript window.

10.  If you can't see a wave window, choose VIEW->WAVE. This opens the wave window. It will be empty without any signals.

11.  To add the signals to it, under Objects window, right click on required signals and select             ADD->TO WAVE-> SELECTED SIGNALS. Then those will be added to the wave window. This can also be performed by typing "add wave *" in the transcript window.

12.  Next we have to assign the values to the signals. Just right click the required signal and choose req option and value for it. All timing by default are in ns

Type	Transcipt command	Procedure
Clock	force -freeze sim:/dffr_pr/clk 1 5, 0 {30 ns} -r 50	right click->clock Offset: 5     Duty cycl: 50 Preiod: 50  rising edge
Net	force -freeze sim:/dffr_pr/preb 1 0	right click->force put desired binary value

The transcript commands for simulating the above DFF code is,

force -freeze sim:/dffr_pr/clk 1 5, 0 {30 ns} -r 50
force -freeze sim:/dffr_pr/preb 1 0
force -freeze sim:/dffr_pr/rstb 1 0
force -freeze sim:/dffr_pr/rstb 0 0
run 50ns
force -freeze sim:/dffr_pr/rstb 1 0
force -freeze sim:/dffr_pr/d 1 0
run 50ns
force -freeze sim:/dffr_pr/d 0 0
run 50ns
force -freeze sim:/dffr_pr/preb 0 0
run 50ns
force -freeze sim:/dffr_pr/rstb 0 0
run 50ns
force -freeze sim:/dffr_pr/preb 1 0
force -freeze sim:/dffr_pr/rstb 1 0
run 50ns

Just copy and paste these lines in the transcript window & hit enter. The waveforms appear in the Wave window. The transcript shown here includes all the possible input combinations of the DFF. Note that the RSTB is the high priority signal, then PREB and finally the DATA.  Here a 5ns offset to clock is added. It is similar to setup time.

13.  To quit simulation, select SIMULATE->END SIMULATION or type "quit –sim" in transcript window

14.  A testbench file can also be used to simulate a code.

15.  For that, both main module and the test bench module has to be compiled. Then simulate the TEST BENCH file and just run for required time.

 

 

 

The verilog testbench file for the DFF is as follows,

       module tb_DFFX;

//assign default values
    reg d= 1'b0;
    reg clk = 1'b0;
    reg preb = 1'b1;
    reg rstb = 1'b0;
    wire q;
    wire qb;
 
    parameter PERIOD = 50;
    parameter real DUTY_CYCLE = 0.5;
    parameter OFFSET = 5;
 
    initial    // Clock process for clk
    begin
        #OFFSET;
        forever
        begin
            clk = 1'b0;
            #(PERIOD-(PERIOD*DUTY_CYCLE)) clk = 1'b1;
            #(PERIOD*DUTY_CYCLE);
        end
    end
 
    dffr_pr UUT (
        .clk(clk),
        .d(d),
        .rstb(rstb),
        .preb(preb),
        .q(q),
        .qb(qb));
 
    initial begin
           #100; // -------------  Current Time:  100ns

rstb = 1'b1;//reset completes
d= 1'b1;
#100;
d= 1'b0;
#150;
preb= 1'b0;
#100;
rstb= 1'b0;
#150;
preb=1'b1;
rstb= 1'b1;

    end
endmodule

 

The transcript for compiling & simulating the test bench file is

vlog {C:/My Projects/dffr_pr.v} vlog {C:/My Projects/TB_DFF.v} vsim -novopt work.tb_DFF add wave * run 700ns

compile DFF compile Test Bench simulate TB without optimization add all signals run upto 700ns

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